If someone has the time, could the take a look at my address decoder logic and verify that it will work. I have included links to the datasheets for the components used.



U1 - 74AC00B
U2 - MM74HC138N
U3 - 74HCT11

I did a quick look and think you may have a logic problem with the IOSEL.

If I decoded it right, you are only decoding IOSEL from $7C00 to $7FFF.
Thats when A10 - A14 are high.

Hope this helps!

Daryl

Oh oops... yes, that is what I wanted anyway - think I have calculated it wrong and not noticed.

It was supposed to have 1K I/O space (which would be 7C00 - 7FFF), as this gives me 8 x 128. Not having a lot of experience, I figured this would be a safe (or huge) 'per unit' space.

Also, I can't source any 8-1 logic gates of any kind. The only one I have found is a 74LS, which I've been told is not ideal / suitable.

One thing I noticed about the circuit, is that simply to decode an IOENx line takes 69ns. If this was running at 14Mhz, that would be an entire cycle delay, and doesnt even include the delay for the IO Device itself.

Is there an improvement that can be made to lower this delay?

As far as 8-1 logic goes, the 74LS(HC)30 is an 8 input NAND gate.

The best alternative I've found is to use a PAL (16V8 or 20V10) to handle all of the address decoding. These have very small propagation delays. The only down side is finding a way to program them cheaply. There is the GALBLAST software and schematic for a hobby-grade programmer available on the WEB, which I am considering.

If you can spare some RAM, then Garth Wilson has used a simple and fast method of decoding EPROM, RAM, and IO. check his Bench-1 computer at 6502.org. Here's the link:
http://www.6502.org/users/garth/project ... chematic=2

Daryl

Sentient,

In you diagram above, I/O selects may be active when you want to read ROM, because A15 never makes it into the I/O-select logic. Having duplicate addresses for things is not necessarily a problem as long as each thing also has its own unique address (and in this case, you don't mind forfeiting some ROM space); but just don't use IOEN8 since it will cause bus conflict with your vectors at FFFA-FFFF which you cannot go without.

Here's the simplest way I can think of at the moment for getting 32KB of ROM and almost 32KB of RAM with the fastest propagation delays. It allows a minimum of 3 I/O ICs, and that number can be expanded at the expense of some more RAM. I'm sorry I don't have a way to post a diagram. I'll try to make this clear with text.

ICs:
74ACT00 inverter
74ACT10 3-input NAND
74ACT521 identity comparator (The '688 is the same thing.)

The '00 and '10 have 9ns maximum (not typical!) propagation delay, while the '521 has a 10ns max.
The inverter can be replaced with a section of the NAND to cut the IC count down to 2.

--> A15 goes through an inverter to ROM CS\ (like you had).
--> A15 also goes to the expansion input (pin 1) of the '521.
--> A14...7 go to the A inputs of the '521, while its B inputs are all tied to +5V.
--> The 521's EQ\ output (pin 19) goes to the CS\ inputs of the I/O ICs (65c22, 65c51, etc..).
--> The I/O ICs will need up to 4 address lines for RS, so we leave A0...3 for that, and connect A4 to the CS input of the first one of those ICs, A5 to the second one, and A6 to the third. (Any more means you'll have to start pulling lines off the '521, starting with A7.
--> For the RAM CS\, use a 3-input NAND section. The 521's output goes to one of the NAND's inputs, the inverter's output (ie, ROM CS\) goes to another input, and phase 2 goes to the last input. The NAND output goes to the RAM CS\.

Nothing is kept waiting longer than 10ns max (5-6 ns typ), including the RAM whose final go-ahead comes from phase 2 through the NAND.

Now you have a much faster solution with only two ICs.

Thanks for the alternative Garth.

BTW - I think you are mistaken in saying I have overlapping addressing.

When A15 is high, the output from U1A is low (enabling EEPROM). This also makes U1B = high, and U3A = low, U1C = high - which makes both RAMSEL and IOSEL high (disabled).

I will see if I can illustrate your IC layout, and get my head around it - sounds a lot better than my existing setup which was thanks to Daryl's SBC schematics.

I'd recommend one of a few options - either swap out the slower chips for faster ones (ie: 74HC138), swap to a lower speed oscillator, or if you really need the speed, go for 8bit's solution of a custom chip.

Many here use the PAL/GAL type chips. I use CPLD's. If you want to continue at 14MHz, you're probably going to need to move to one of these custom chips to maintain the lowest propegation delay. Most of these chips have propegation delays of between ~3.5ns to 25ns with most at 5ns to 15ns, and you can replace a lot of IC's by using one of these chips.

The programmer is a problem as mentioned before.

I use MAX 7000 series CPLD's from Altera 'cause their software is easy to use (all graphical, you can do VHDL if you know it, but if you don't you can just plunk down AND gates and OR gates and connect them like any other schematic and the software will generate the appropriate files to create your logic - only downside is that the IC's are not DIP's, they are PLCC's, QFP type packages and BGA type packages)

_________________
-Tony
KG4WFX

> I think you are mistaken in saying I have overlapping addressing. When A15 is high...

Oh yes, my mistake.

Take a look at the possibilities with the '521 though. Nothing there has to wait more than 10ns. You'll have only one more IC than the programmable-logic option, and you don't have to worry about it erasing itself after 10 years if you want to use it a long time. In my brief exposure to CPLDs a few years ago, manufacturers were only guaranteeing 10 years without self-erasure, which made my reluctant to put one in one of our products since they tend to get used considerably longer.

Taking your ideas into consideration Garth, I have made up this decoder. Comments??



Related Datasheets

74HCT688
74AC00B
MM74HC138

Sentient: What speed are you planning on running this thing?

Garth: you are right, many CPLD's have a life of 10 years, the range I've seen so far is 10-40years depending on the part. According to Altera, the one I am using lasts up to 20 years (I don't know if I believe them, I always figured about 10 years which I felt was fine for my little project, The reason I don't know if I believe them is that when I called them a while back to ask since I couldn't find it in the datasheet, they said about 20 years, but I don't know where they pulled that number from).

_________________
-Tony
KG4WFX

> Taking your ideas into consideration Garth, I have made up this decoder. Comments??

The point in using the '521 or '688 is to eliminate the '138 partly to reduce the parts count but primarily to keep the delays to a minimum, without eating into the RAM space as much as I did on my workbench computer. You can get rid of the '138 because the 65-family I/O ICs have both a CS and a CS\, and they both have to be true in order for the device to be selected. That way you can run your IOSEL\ to the CS\ on all of these ICs, and then run one of the address lines to the CS of each. My schematic linked in 8BIT's first post above is my complete address decoding for my workbench computer. People commonly think there's more that is not shown in the diagram; but it's all there. For yours, I suggested using the '521 or '688 because you wanted the RAM to be closer to 32K.

Your way will waste less RAM space than what I'm suggesting; but depending on the number of I/O ICs, the percentage of difference won't be very much. So since you want the high clock speed and short delays, I would suggest going with the faster method with no '138. (Of course ultimately you can do it however you want. I just want to make sure you really did understand the options first.)

And speaking of number of I/O ICs needed-- The 6522 VIA allows for a lot to be done with a single IC too. One of the 3 VIAs on my workbench computer is used for 7 things at once: keypad, LCD, printer interface, beeper, RTC, I2C, and a dumb synchronous serial interface. My next workbench computer will do even a lot more with a VIA.

Note that you do need to run the phase 2 into the NAND for RAM select for dependable operation without memory leaks resulting from a timing problem, which is why I indicated the tripple 3-input NAND instead of the quad 2-input NAND.

The reason I put in the '138 was because with your system (if I understand it correctly), it would be possible to enable all 3 I/O's at once, by enabling lines 4,5 and 6. It would also leave gaps in the IO space, and having 8 expansion slots was something I wanted as I liked the idea of a semi-plug-n-play system.

Also, I'm not looking for speed. I actually plan on running my system at 1 or 2 Mhz to start with. I'm sorry if I gave the wrong impression when I mentioned that earlier - I just meant to point out the observation I had about the timing speed being close to one 14Mhz cycle.

The reason I left the PHI2 signal off the NAND gate, was because in other examples Ive seen it is NAND'd with the R/W signal and I was planning to do the same. Is this not a recommended practice??

I remember seeing a post you made (but damned if I could find it at 12:30am) about the correct way to use PHI2 to enable access - since I couldnt find it, I thought I would use the idea I could find.

> The reason I put in the '138 was because with your system (if I
> understand it correctly), it would be possible to enable all 3 I/O's at
> once, by enabling lines 4,5 and 6.

You can if you want to, but I've never done it. One application might be if you wanted to set up more than one VIA the same way at the same time, shortening your program. Each I/O IC does have its own unique addresses too though, so you can talk to one at a time, or any combination at the same time.


> It would also leave gaps in the IO space, and having 8 expansion slots
> was something I wanted as I liked the idea of a semi-plug-n-play
> system.

The only way to avoid gaps in the I/O space would be to have exactly the number of addresses that each IC has registers. If you use the same kind of decoding for everything and then have two 6522 VIAs (with four addresses each) and two 6551 ACIAs (with two addresses each), at least the ACIAs will waste some space. The waste is so minimal so as to be insignificant though.


> Also, I'm not looking for speed. I actually plan on running my system
> at 1 or 2 Mhz to start with.

At that speed you can get away with murder. In fact, why not experiment with a window into another megabyte or two of paged memory.


> in other examples Ive seen it is NAND'd with the R/W signal

That's fine, as long as RAM gets phase 2 brought into the R/W\ but the VIAs do not. RAM must not be allowed to write when phase 2 is low. The 6522, 6551, 65xx I/O ICs have their own phase 2 input, and the selects must be valid before phase 2 goes up or they won't work right, regardless of whether you're reading them or writing to them.