[
apologies for anyone who read this earlier and now it's changed: the more I looked into this the more I learned/discovered the more I updated the post - sorry for any confusion]
I think I might have figured out the problem with the VIA not working:
Going by the decoding that currently exists in my project (see attached image), wouldn't the RAM and VIA enable at the same time?
Decoding process:
For
/ROM selectRequired address bus pattern: 1xxx xxxx
IC6C receives logic 1 from A15 and logic 1 from +5V rail
Active range: $8000-$FFFF
For
/VIA selectRequired address bus pattern: 0xxx xxxx
IC6B receives logic 1 from A14 and logic 1 from IC6C if A15 is logic 0
Using A0-A3 for RES0-RES3
Active range: $4000-$400F
For
/RAM selectRequired address bus pattern: 0xxx xxxx
IC6A receives logic 1 from CLK (when high) and logic 1 from IC6C if A15 is logic 0
Active range: $0-$7FFF
Problem 1: Basically, the RAM will be enabled unless A15 is logic 1. This means that the RAM and VIA (and the ACIA that I was planning to put in) will be enabled below address $8000. The VIA address is at $4000... and so we have bus contention
.
Now, the /OE of the RAM chip is hooked up to A14. This will prevent a read if the VIA get selected (using A14), but what about writes? I don't know quite enough about bus contention. Does it happen during writing as well? From what I understand at the moment it would.
Problem 2: Like a twit I thought that the beginning address for the VIA was $6000. It's not - it's $4000 (binary 0100 0000). It changed when I followed advice and used (faster) NAND gates instead of a 3-8 decoder
.
Does everyone concur with the above?
If so then I just have to figure out some slightly more complicated decoding. If I can't figure out how to do it with gates then I'll use the (albeit slower) 3-8 decoder.
[edited to add extra info]
Ok, if I need to, I can put an OR gate in the RAM /CS line (
/RAM select). One of the inputs will be the
/RAM select and the other the
/VIA select.