Thought it would be useful to have a new topic for this. See
this doc by David Empson (also
here). Refer also to
the '816 datasheet (
newer).
From
Brett Tabke's document (also
here):
Code:
=====================
Appendix C: IC Pinouts
=====================
/=============\ /=============\
VP I1 40I RES Vss I1 40I RES
RDY I2 39I VDA RDY I2 39I o2 (OUT)
ABORT I3 38I M/X o1 (OUT) I3 38I SO
IRQ I4 37I o2 (IN) IRQ I4 37I o2 (IN)
ML I5 36I BE NC I5 36I NC
NMI I6 35I E NMI I6 35I NC
VPA I7 34I R/W SYNC I7 34I R/W
VDD I8 33I D0/BA0 Vdd I8 33I D0
A0 I9 W65C816 32I D1/BA1 A0 I9 6502 32I D1
A1 I10 31I D2/BA2 A1 I10 31I D2
A2 I11 30I D3/BA3 A2 I11 30I D3
A3 I12 29I D4/BA4 A3 I12 29I D4
A4 I13 28I D5/BA5 A4 I13 28I D5
A5 I14 27I D6/BA6 A5 I14 27I D6
A6 I15 26I D7/BA7 A6 I15 26I D7
A7 I16 25I A15 A7 I16 25I A15
A8 I17 24I A14 A8 I17 24I A14
A9 I18 23I A13 A9 I18 23I A13
A10 I19 22I A12 A10 I19 22I A12
A11 I20 21I Vss A11 I20 21I Vss
\=============/ \=============/
Quote:
Notes:
ML: Memory Lock line (pin 5) is asserted low during the execution of
the read-modify-write (asl,dec,inc,lsr,rol,ror,trb, and tsb
instructions to inform other ics that the bus may not be claimed
yet.
VP: Vector Pull is asserted whenever any of the hardware vector
address's are being accessed during an IRQ.
Abort: An input. When asserted caused the current instruction to be
aborted.
VPA/VDA. Valid Program Address and Valid Data Address. These two
signals extend on the 6502 SYNC line - to better handle
DMA schemes.
VPA VDA
0 0 -Internal Operation
0 1 -Valid program address
1 0 -Valid data address
1 1 -Opcode fetch
M/X: Memory and Index lines. These signals are multiplexed on pin
38. M is available during phase zero and X during Phase one.
These two signals reflect the contents of the status register
m and x flags, allowing other devices to decode opcode fetches.
E: Emulation pin. This signal reflects the state of the processors
emulation bit (E).
See also
this topic on the use of the '816 in emulation mode.
To use the '816 in a 6502 socket, you will need an adapter:
- pin 1, VP, is now an output and should be no-connect
- pin 2, RDY, is now bidirectional if the WAI instruction might be used
- pin 3, ABORT, is now an input, and there is no clock output
- pin 5, ML, is now an output (was previously no-connect)
- pin 7, VPA, is not the same as SYNC. Use VPA and VDA if you need SYNC.
- pins 26-33, D7-D0, are now outputs during phi1, no longer undriven during phi1. A bus transceiver might be needed to avoid contention
- pin 35, E, is now an output (was previously no-connect)
- pin 36, BE, is now an input, should be tied high
- pin 38, M/X, is now an output (was previously SO input)
- pin 39, VDA, is not a clock output, and there isn't a clock output
I'll update this post if need be. Comments welcome!
Cheers
Ed
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