Hi Peter,

I have never used or even seen that style of wiring ... I believe that you called it Verowire?

It looks tidier than point-to-point wire wrap, but it occurs to me that a significant percentage of your wires are very parallel and close to one another (perhaps only a couple of mils in some instances). Which brings me to my amateur question of the hour: Is potential 'cross-talk' a concern when using this technique? I am aware that we're dealing with micro-amps in most cases, but at high frequencies, I would find myself worrying about noise.

Mike

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I don't have a problem admitting that my experience is limited. I'm just harking back to a lower-division physics class, where we were taught that mutual inductance between two or more conductors was proportional to the current (or was it delta current?!?) and inversely proportional to the distance. Would capacitance be a stronger noise factor than inductance in a case like this? The theory is rather dusty in my head (~28 years worth).

Mike

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

But you can run a couple of MHz at least, using verowire. All these effects are there, but they not be as bad as you fear.

Wirewrap is a much better choice for prototyping. So much so it is worth the initial investment in the tools necessary IMO. I've had 6502 FPGA softcore wirewrap project running at 38MHz for a certain 5x7" TFT display with an ss1963 chip making graphics years ago. And the only reason it was limited to 38MHz was because of the limitation of the ss1963 graphics IC driver.
Nonetheless, the attention to detail of this project is excellent! Especially the power rails.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi Mike,

its called "Verowire" or "Road Runner" (depending on the manufacturer). Cross-talk is not an issue when you have a good ground and for the frequencies in this project. Wires are very thin (34 AWG) and if you plan the placing of the ICs the wires are rather short, so the coupling capacitance is small. When placing wires you try to avoid zig-zag and hence the inductance stays low as well. Why I use Verowire? Because when I started doing larger projects about 30 years ago wire-wrap was out of budget, I would have loved to use wire-wrap then. Now I'm used to it and it's still cheaper than wire-wrap, especially as you can use normal through-hole sockets. PLCC is a bit difficult to plan as you must first solder the outer pin, once the inner pins are soldered it's almost impossible to make changes to the outer pins wiring.

Peter

For those interested, I have posted some preliminary schematic of my SBBC here http://forum.6502.org/viewtopic.php?f=4&t=2911&p=32760#p32760. Together with the schematic of the VGA controller already posted this is as far as my SBBC is working.

Could you please post a monochrome version for the benefit of partially color-blind old dinosaurs?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

BDD, do you need help with an image manipulation program? I recommend Imagemagick.

Better yet, try a bookmarklet, such as this one found at https://coderwall.com/p/k4wrzg

Just drag and drop to your bookmarks bar and rename to "greyscale" or whatever you see fit.

Cheers
Ed

Ed, you should have more respect for elder people

Here go the BW pictures (my good deed for the day) and even with update to the IO Extension part.

(Hey, I'm getting on to be an older person myself! When people send mails with large fonts, they've misunderstood their tools. The mails they receive will still have normal-sized fonts. They should be setting their browser to use larger fonts. Same, to my mind, with vision problems - there are accessibility tools, and there should be. People who need them should use them.)

It's not the color per se, but the lack of contrast that makes it difficult, especially with greens and blues. The image tools are of very limited help in that regard.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Two comments: 74HCT and dual 2691s.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hi BDD,


so I can still surprise you . But there is a reason for both points. The HCT (except for the HC138 in the IO-Extension, which is an error) are put at places where their speed is not the limiting factor. The ' 259, '175 just need to latch data that is present for at least 60ns, this is by far more than the minimum setup time. The '251 the same for getting D7 valid. The '595 is a little bit more critical, absolute maximum ratings would fail. But typical performance is sufficient for the current clock speed. So I used my old stock of HCT to build this part as I had no AC(T) devices (and for the '595 it does not exist). Still the design was for 6MHz and now at 8MHz it runs perfectly.

As for the dual 2691. At the moment there is only one installed. The reason for the dual 2691 is a rather lengthy story. First I planned to use W65C51, then I read about the bug. So I omitted serial ports at all on the main board. Then I started to build the computer and designed the power rails in a way that only three rows allowed 600-mil DIP cases and I used them all. Then I read about the 2691 and 2692 and thought very good, the 2691 is available in 300-mil (and did not read your post in more detail), so I reserved the space for it. Going back to an additional 600-mil row would have been a waste of space in the already cramped layout. At the end I had space for another 28-3 DIP case and planned to use it for another 2691. But I might drop this again.

You may think "bad planning" and you are right, but I wanted to start building the computer as it had many hen and egg problems and so I wanted to build up my experience as I built each block. The good side is, I learned a lot and it works better than expected