Back here Dr. Jeff mentioned a thread I started on Oct.26, 2010. I was very new to Xilinx CPLDs and even newer to FPGAs, as I hadn't an inkling to HDL. I was still using schematic entry... Long story short!:

That thread was more geared towards older Spartan 2 devices which were 5v tolerant, and all I did was assign all the HDL pins out to an IOB pin. 5v is dead where FPGA's are concerned, let's face it!

I'm thinking of starting a new thread around the 3.3v Spartan 6 144-pin TQFP device which I have been working with for almost 2 years now and have some experience in.

For an 8-bit 6502 core the blockRAM could easily fit the zero-page and stack-page RAM inside the device.
I guess for the core comparison tests, it would be wise to max out the remaining blockRAM for the "OS" boot ROM. So in similar fashion to the first endeavor, all pins from the cpu and all internal blockRAM's would be assigned to the Spartan 6 IOB pins.
I would be utilizing ISE14.1 in this test.

Some effort would be necessary by me, I would have to redo the whole testing... I have all the original HDL from the cores mentioned in that thread burned to CD.
What is irritating to me is that all the pic's I had posted to photobucket are gone, so that thread has effectively been rendered useless.
Since this website has been updated by Mike N., photo attachments can now be made direct to this site.

What do the people say?

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

Hi EEye
I think a re-run on spartan 6 is a fine idea, and I welcome it!

But I'm not quite sure what you're saying about the block rams being connected to the pins. I would expect the data and address busses to connected to pins (to allow for off chip expansion) and the block rams to be hanging off the busses internally. Having said that, I would generally expect the speed-limiting critical path to be inside the CPU - in the ALU, or the decode, most likely.

Cheers
Ed

(Edit: BTW, some of the smallest microcontrollers these days have 20k to 40k of memory, with no scope for external expansion, so a design which only uses on-chip memory is still a reasonably useful thing)

You're correct, I misspoke there sorry. No internal BRAM lines brought out to IOB pins.

It would be nice to have the decoding done the most efficient, applied identically across all cpu comparisons.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

I had mentioned doing this around the 144-pin .5mm version, but I was considering the 256-pin 1mm BGA version as well. I'm designing a new board that will have the BGA style.
1 member here, enso, has mentioned that the BGAs were actually easier to mount. They have more resources as well.

Also, since I have the 10 original cores in that thread and hopefully all their license agreements I will see if I can make them attachments as well. Of course we also have a few more additional cores to add.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502