LOL thanks. I should have known they'd be on the site!

Would you mind casting your eyes across my revised circuit diagram? In particular, the connections on the W65C02S.
Also, I'm thinking of replacing the CY7C199CN RAM chip (IC7). Which modern equivalent would you suggest which would work well with a 65C02 system?

<URL removed as no longer valid>

Notes:
- PHI2C should read PHI2O.
- NMIB and IRQB will be hooked up at a later point in time.
- The memory decoding is staying as it is for the first version of this project, but subsequent ones will have the NOR gate setup.
- The button circuitry has been excluded for clarity

Thanks guys!

I can't take time to go through it in detail until later today, but I will comment that you must not allow the RAM to get written to when phase 2 is down. The address is not guaranteed to be correct before R/W\ goes low, especially with gate delays in the address decoding; so it is imperative that you make the RAM wait until phase 2 rises. Preferably you make it so its WE\ cannot go low when phase 2 is low, but you can also make it so the RAM's CE\ won't go low until phase 2 rises, which will be fine at your low clock speed. This is mentioned in the address-decoding page of the 6502 primer, and in my "Tip of the Day" column.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi

How about putting in an a NAND gate on the /CE line going into the RAM IC? That is fed by the two inputs:
A = 74HCT138N decoder chip Y7 line which activates the RAM
B = PHI2, fed through an inverter first

I.e.:
<URL removed as no longer valid>

I'm still reading may way through the addressing info atm.

IC8A there is the wrong kind. What it needs to be is that if either input is high, the output will be high; IOW, it needs to be an OR gate, not a NAND. What he has there is that RAM needs to be deselected (Y0 high) at the '138 and phase 2 has to be low in order to select the RAM. It won't work that way.

RAM tends to be the fastest thing on the bus, and you're not running a high clock speed anyway; but otherwise I would encourage keeping the glue-logic delays as short as possible, and, if you really must use a '138, it might be worth having a second one and running phase 2 into its G1 input to avoid the delays of the extra gates. This second '138 then will only get used for RAM (and possibly other things that need phase 2 brought into the write enabling), and the first '138 would get used for other things like the VIAs. The difference in the input connections of the two 138's is that one has phase 2 on its G1 input, and the other does not. Their A, B, and C inputs would go to A13, A14, and A15 on both.

The logic shown on the 6502 primer's address-decoding page will get you more memory and tons of I/O with fewer parts and less gate delays though. The really basic whole-computer schematic at http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU reflects this too.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

You should not use Ø2 to gate chip selects—only use Ø2 to qualify RWB.

The 65C02's address bus becomes valid about midway through Ø2 low, at which time your glue logic should assert the appropriate chip select. When Ø2 goes high that is the time to assert the /OE (read) or /WR (write) input of the selected device. Note that this arrangement is required if using 65xx family I/O devices (e.g., 65C22).

The idea behind asserting the chip select during Ø2 low is to give the selected device plenty of time to get read for the read or write operation. If you wait until Ø2 is high to select the device, part of the high cycle is expended in activating the device, leaving less time for the read or write operation to be completed. This is not a critical timing issue at slow Ø2 rates (to quote Garth, "You can get away with murder at 1 MHz."), but does become critical if you bump up the clock speed. Your best bet is to always use the proper method regardless of speed.

Note that the 6502 family data bus is never valid when Ø2 is low, regardless of the state of RWB. Allowing a write to occur during that time could result in a wild access to a device, possible corrupting memory contents or I/O device registers.

On another note, if all of your silicon is CMOS you don't need 74ACT or 74HCT logic. instead, use 74AC or 74HC parts. You only need the 'T' parts if a 74LS device is driving the CMOS device input. Note that 'T' and non-'T' CMOS device outputs behave the same within a given family.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The 74AC138 has a worst-case prop time of 10ns on 5 volts. Of course, as you note, cascaded logic can quickly build up prop time to an unacceptable level. Incidentally, the 74HC138 is substantially slower than its 74AC sibling.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

which is why I said, "Preferably you make it so [the RAM's] WE\ cannot go low when phase 2 is low, but you can also make it so the RAM's CE\ won't go low until phase 2 rises, which will be fine at your low clock speed." Again, RAM is available in speeds faster than any other part of the computer, down to 8 ns, so early qualification is not really needed until you get into the highest speeds, say at least dozen MHz. My workbench computer doesn't select RAM until phase 2 goes up, and runs up to 7MHz with 4MHz parts and 55 SRAM. I'll do things differently though when I try for 25+MHz.


Actually, the '22 requires that its R/W\ input be valid before phase 2 rises. It has no OE\ of course, as it has the phase-2 input.


That's particularly true if you use a transparent latch for an output, where it could be a problem if the output experiences glitches during the phase-2-high time. The processor is not guaranteed to have the data correct on the bus until tMDS time (at least 25ns for a 14MHz part) after phase 2 rises though; but fortunately as long as the address is correct, most devices won't care what the data is until their setup time before de-select. Before their data setup time, the data could be wild and it won't matter. The important thing is to make sure no writes can be done until after the address is valid and stable.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I didn't quite word that right. My point was that chip select, RW and the address inputs to the 65C21, '22 and '51 must be valid before the rise of Ø2.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hi guys

After doing a bit more reading (mostly the great articles/guides here!) I've decided to dump the decoder chip as you suggest and go for the NAND gate setup.
I've also pinched your button de-bounce circuit (something I intended to include, but hadn't put in until now) and added the power regulation circuit.
Another change is that I've managed to obtain a couple of 62256B SRAM ICs so have taken out the CY7C199N and put one in it's place.

Here's the latest version:
<URL removed as no longer valid>

[EDIT] One additional thing: Although I've got the usual 100nF decoupling capacitors, I haven't yet put in a larger smoothing capacitor. I've got a 22uF Tantalum. Would that do? I understand Tantalum is much quicker to react than standard electrolytic.

It's hard to catch every detail with a quick look, but it does look mostly like what I've been using for 20 years without problems (except that I have 3 VIAs and 3 ACIAs).

Tantalum capacitors do have lower ESR (equivalent series resistance) and better high-frequency performance than electrolytics do, and OS-CON capacitors are that much better again. OS-CON is a type of capacitor made by at least a couple of companies. They look similar to electrolytics but they're better than even tantalum. You probably don't really need to worry abou it for this though. If you were designing a switching regulator, then yes, I would recommend OS-CONs.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I've got to admit that part of the reason I was hanging on to the decoder was that my design would look almost exactly like yours otherwise - not a great surprise since I've gotten so much help here and borrowed bits and pieces all over the place. I suppose even if I can't say that it's entirely mine, it's been a huge learning experience so far for me if nothing else!

BTW regarding the 22uF capacitor: I read somewhere (I wish I could remember the site) that there's a good reason or two not to put the larger cap in, although everywhere else it says it's to compliment the small/faster 100nF. I.e. the 22uF is slower, but has a greater capacity and so the two sizes/types together make up for power fluctuations: 100nF for smaller/faster ones on ICs, the larger/slower one for general power supply dips. Is my understanding correct?

The only reason I know of not to put a bigger bypass capacitor in for any given situation is that physically larger ones tend to have more inductance. Dr. Howard Johnson, industry guru in high-speed digital design, says to just use the largest capacitance that available and economical for any given package size. My power distribution is from the middle of the board, like a star, and there's a 150uF OS-CON there, along with a bunch of .1's.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

(I'd say I've also seen the story somewhere that a large slow capacitor complements a small fast one.)

To quote prof. Farnsworth: "Good news, everyone!"

My 6502 has finally been built! Well, mostly built . I haven't hooked up the 6522 yet, but I've got the CPU, EEPROM, RAM and glue circuitry together and it is doing something on the bus. Also, thanks to Garth, I've now got the single step button working so will go through and see if it's actually functioning correctly tomorrow.
In the meantime here's some pics. I warn you: It doesn't look pretty! I had to use some rather ratty components as I've run out... plus it's my first attempt at anything like this .

6502 project with 2MHz oscillator can:
<URL removed as no longer valid>

6502 project with single step (oscillator can removed):
<URL removed as no longer valid>

Scope out with oscillator plugged in (the scope can't read 2 MHz unfortunately - but it shows activity):
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Finally: Thank all of you for your tremendous assistance in helping me get this far!