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PostPosted: Sat Feb 15, 2014 11:03 am 
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GARTHWILSON wrote:
16F72. The SSP is the same across many variations though. I think I tried sending dummy data (like CLRF SSPBUF), but I don't remember for sure. Whatever is in the shift register there whould get sent anyway, as the clock is controlled by the master, not the slave.
I'll download that Datasheet. Years ago I vowed to avoid devices with only an SSP module instead of an MSSP module for some reason.


Last edited by Michael on Sat Feb 15, 2014 11:15 am, edited 1 time in total.

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PostPosted: Sat Feb 15, 2014 11:14 am 
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Klaus2m5 wrote:
If it is for slave selects of an SPI interface there is another option. Have you ever looked at a 3 to 8 decoder chip?

The 74HC137 seems to be ideal as it has a latch with low strobe (GL) and decodes 3 bits into 8 with enable. So you could have $x0-$x7 selecting the slave and any of $x8-$xF disabling the slave select (A-C=A0-2, G2=A3, G1=1).
I'm familiar with the '138/'238 and '139 but I've never looked at the '137. Thank you. I'll grab the Datasheet.

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However, as with the 573 data must be valid for the whole duration of chip select but CS is now active low. A chip select to write a latch is not required to be active for the whole duration of PH2, but for any time inside the period where data is valid. So a short strobe generated by the PIC will do.
This deserves a closer look. Thank you, Klaus.


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PostPosted: Thu Feb 20, 2014 10:35 pm 
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http://www.alldatasheet.com/view.jsp?Se ... d=74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES

I've never seen them listed anywhere, though.

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PostPosted: Fri Feb 21, 2014 3:03 am 
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richardc64 wrote:
http://www.alldatasheet.com/view.jsp?Searchword=74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES

I've never seen them listed anywhere, though.


http://octopart.com/partsearch#!?q=74als996

I guess they're easier to find than you thought :-)

===Jac


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PostPosted: Wed Feb 26, 2014 11:16 pm 
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I use a 573 in my Orwell machine as a simple addressable 8 bit latch. I have eight LEDs on it and use it for debugging (and doing silly Larson scanner things). There was just a little logic needed to handle the positive chip select and I think from memory I just address decode it the same as if it were normal RAM (so phase 2 is involved). I can check when I get home. It seems to work fine but maybe that's because I am running slowly, only 1Mhz, so the timing just works.

Simon

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PostPosted: Fri Feb 28, 2014 3:23 pm 
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richardc64 wrote:
http://www.alldatasheet.com/view.jsp?Searchword=74ALS996
8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
If you want an output port whose contents you can read back, one very simple solution is to use a '574 but arrange the decoding such that RAM is not inhibited when the port's address appears. I think of this as causing the '574 shadow what's in that bit of RAM. But however you like to think about it, the upshot is...
  • writes go to the '574 and RAM
  • reads cause the RAM to return the last value written :D

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