This forum can be used to ask questions regarding any hardware projects, correct? If not, I apologize in advance, but since this forum has a number of people who have designed hardware professionally, I feel comfortable asking my question here. Besides, the answers I get to my question here
could be incorporated until my little 65816 project (still designing/balancing life, etc).
On the Vintage Computer Forums (VCF), one of my current projects I wanted to do was to create a Low-Level MFM Format Utility for DOS- mainly because I'm sick of programs not returning useful error code information when LLF inevitably goes wrong... MFM hard drives are among the most fickle of vintage hardware, IMO. Part of my application, I wanted to detect bad tracks after formatting by writing test patterns to disk, and seeing which tracks return an error. And that means I need to understand FM and MFM encoding, and how both of them remove the clock signal line.
Well, long story short, it turns out that in my Digital Communications class (Not bashing the class at all- professor was awesome, and there was a lot to cover.), going through my notes, I can't recall us going over the prerequisite to even FM encoding- Non-Return-to-Zero Inverted. Before I go on to MFM, I want to devise a hypothetical circuit that can decode an NRZI stream with a
separate clock signal, put it into a shift register. I don't actually care where the NRZI stream comes from- just that the shift register's serial input is connected to the output of an NRZI decoder, and the shift register's "clock" is connected to the clock from the NRZI stream.
Like a real MFM decoder seen on controller ISA cards, I imagine this would entail two separate clocks (except in FM/MFM, the clock is recovered from a signal which carries both and clock data)- one strictly for the NRZI stream and shift register, and the other for any support circuitry attached to the shift register's parallel output, the latter which is shared with the microprocessor. To make this 6502 related, let's assume the microprocessor is a 65816 attached at to the shift register parallel output at 0x00:0x8000 (unlatched)
.
NRZI is simple enough to understand- a transition at the
leading edge of the current bit clock represents a logic 1, and no transition represents a logic zero. I even found a simple encoder/decoder circuit
online. The issue I'm having with incorporating this little circuit hypothetically is that I have to somehow use a negative edge clock for the shift register, and I lose half the period for waiting for the transmission line to settle (more, if I use an inverter on the clock input to the shift register). Data therefore becomes ready "out of sync" with the NRZI clock, and I can imagine scenarios where the shift register is ready, but by the time other circuitry is ready to read the parallel output (i.e. leading edge of microprocessor clock), the positive edge of the NRZI clock has already elapsed, and the data on the parallel output is invalid.
I do not know offhand if a shift register with latched output prevents this problem.Since I'm dealing with two separate clocks, what is a good way to ensure that when the 65816 or other circuitry reads the shift register after 8-bits clock in, the output value from the shift register will not be invalidated by the NRZI clock positive edge by the time the settling time and leading-edge for the circuitry connected to the microprocessor clock has elapsed?