Idea for 6502 system

Rey_Morta · Post by **Rey_Morta** » Mon Dec 27, 2004 6:50 pm

I have been thinking on making my own portable 6502 based system.This is the basic layout for it.

Specs: RAM 32K,ROM 16K, I/O 1-4 W65C22S

Peripherals:
DIOS Ultra: PS/2 keyboard,LCD 40X4, RS-232 terminal, I2C EEPROM

Power:
AC: Old PC power supply
DC: RC car battery 9.6 Volts 1600 milliamp OR 4 volt 5 amp lead acid battery (x3)

Memory Map:
0000-3FFF RAM 0
4000-7FFF RAM 1
8XX0-8XXF I/0 0
9XX0-9XXF I/0 1
AXX0-AXXF I/0 2
BXX0-BXXF I/0 3
C000-FFFF NVRAM

Notes:
W65C02s,W65C22s (I/O 0),NVSRAM 16k X 8, SRAM 16K X 8 (X2)

I/0 0, 6522: 6502 <-> DIOS interface <-> terminal
I plan on using a micro controller to handle the terminal I/O and ermanent storage.

I/0 1-3: Future expansion

Software: EhBASIC

From what I have seen it is best to use AC and ACT chip's for speed. I would like to have it run at 10mhz or more. I don't think that I will be having a problem designing a power supply. I may have some problems with the clock design but there are enough posts about that I should be able to work it out with some local help. I plan on doing switching so that I can use either the keyboard/LCD or rs-232 for the console. I have yet to deside on weither to use interupts or polling to get console input.

From what I have found it is hard if not Imposable to get 16kx8 sram.

Which would be the most effective way of dealing with this:

1. Use half of 3 32kx8 chips

2. Use a bunch of 8kX8 chips

3. Use 2 32kX8 Chips and a OR gate.

or is there a better option?

What is the slowest RAM/NVSRAM I could use and still be able to meet the timing requirements for 10mhz?

GARTHWILSON · Post by **GARTHWILSON** » Mon Dec 27, 2004 7:56 pm

AFAIK, 16Kx8 SRAMs have never been made. My current workbench computer uses half a 32Kx8.

Remember that the 6502 basically does a complete read or write in half a clock, or 50ns @ 10MHz, and some of that time will be taken by set-up time and glue logic propagation delay. Your RAM should be 35ns or faster, which is getting easy to find. (E)EPROM and probably even NVRAM OTOH is not easy to find in those speeds; but if it's read-only as far as the 6502 system is concerned, you don't need to gate it with phase 2, so that buys you some time. 55ns may be borderline fast enough for consistent operation. One way to get around the problem of slow boot-up memory is to start at a slower clock speed and have the compuer copy the boot-up non-volatile memory to faster SRAM before kicking the speed up.

It is normal for those new to the particular field to go overboard with address-decoding logic and make it too complex and end up with horrendous propagation delays. You can get all the memory you want and even lots more I/O with an address-decoding scheme like the one in the middle of the address-decoding page of the 6502 primer. Actually the whole thing could be done with a single 74ACT00. I have 32K of ROM and 16K of RAM, but with a small change in the circuit you can get 32K of RAM and 16K of ROM just as simply. Note that the I/O addresses will not end up on evenly spaced boundaries. (See the workbench computer page.)

One idea for my next one (if I ever get around to building it) is to have 65,280 bytes of 10ns RAM, only 256 bytes for I/O space, and no ROM in the actual memory map. The OS will have to be loaded into the fast SRAM before the main processor comes out of reset. With a couple of tricks, the address-decoding scheme is almost as simple and fast as the single-74ACT00 method above.

One of the 6502's greatest strengths is in interrupt performance. I take advantage of that and run a lot of things on interrupts. Your RS-232 port should be run this way. See my interrupts primer.

The PC keyboard interface is almost the same thing as I²C, so you can double up, making the I²C port available when the PC keyboard is not being used.

Rey_Morta · Post by **Rey_Morta** » Mon Dec 27, 2004 11:45 pm

It took me 20 mins of stairing at you address decoding diagram to figure out what you were doing in it. I always thought of alocating addresses for I/O in terms of blocks of memory that needed to be access individually. When I first saw:

Quote:

a13->cs1 of via1
a12->cs1 of via2

the first thing to come to mind was "What about r/ws to XX11 XXXX?" 20 mins later I relized "If you program right it never happen!"

I am going to try to adapt my idea around that set up.

As for the memory I was orginally planning on using the microcontroller to load data into the upper memmory from the I2C EEPROM. I would just need to get ahold of a couple of PCF8574's to do it.

Is there anything else I need to keep an eye on like distances from the CPU to RAM, ROM and IO?

On a side note isn't there a simple circuit that can be used to make a battery backup for normal SRAM?

GARTHWILSON · Post by **GARTHWILSON** » Tue Dec 28, 2004 9:10 am

Quote:

the first thing to come to mind was, "What about R/Ws to XX11 XXXX?" 20 mins later I realized, "If you program right, it will never happen!"

Not accidentally anyway. If you had two VIAs that you wanted to set up identically, the scheme does allow you to write the same information to both at once; but so far I have never had any occasion to do so. You should give descriptive names to the addresses and then only use the names in the assembly-language instructions and let the assembler fill in the numerical addresses.

Quote:

Is there anything else I need to keep an eye on like distances from the CPU to RAM, ROM and IO?

At 10MHz and up, keep the distances as short as you can. You'd do best to have at least a ground plane, if not power on one side and ground on the other. I'm assuming you're wire-wrapping, which allows you to put the sockets shoulder to shoulder for maximum density and keep connections short and direct. Prototyping perfboard is easily available and inexpensive with a ground plane on one side. You shouldn't have any trouble at 10MHz if you build this way. It gets quite a bit more expensive if you want a plane on each side plus plated-thru holes.

Be sure to bring phase 2 into the RAM select but not into the VIA selects. The address lines are not guaranteed to be valid and stable before R/W\ goes down, so writing to a wrong RAM address during phase 1 is quite possible if the RAM is selected and R/W\ is down. The VIAs OTOH will not work right if the CS pins are not valid before phase 2 rises.

Quote:

On a side note isn't there a simple circuit that can be used to make a battery backup for normal SRAM?

I'm sure you could find something from Maxim http://www.maxim-ic.com . I did a design 16-18 years ago with cheap parts, but there were quite a few parts involved. It was less than ideal from that standpoint, although it worked fine. I also have an extremely simple design here that appeared on page 122 of EDN, 10/9/97. [Edit: See viewtopic.php?f=4&t=573&p=32004#p32004 for the diagram.] It uses a 3.6V NiCad battery, a resistor, an NPN small-signal transistor, and a diode. When the power is on, the SRAM gets the full 5V, and there is nothing to delay any of the digital signals. I don't have any way to E-mail it to you, but I could either photocopy it and mail it to you (I'd need an address) or just describe it in text if you prefer. Ideally the SRAM would get locked out just before the processor's power starts dropping, to protect the SRAM from possible flaky operation when the processor's power supply voltage has dropped into a range of unreliable µP operation. This simple design from EDN unfortunately does not appear to offer any protection for that part-- only for protecting the data after the power is already down. But if your reset circuit has brown-out reset, then this simple back-up circuit will do fine.

BigEd · Post by **BigEd** » Sun Feb 23, 2014 4:45 pm

Hi Garth, now that we have attachments, would you be so good as to scan that article?
I found the text, but not the diagrams:
http://www.edn.com/design/other/4341478 ... OS-devices

"sprow" reckons a couple of diodes are enough: http://www.sprow.co.uk/bbc/hardware/epromemu.txt

Cheers
Ed

Michael · Post by **Michael** » Sun Feb 23, 2014 10:04 pm

GARTHWILSON wrote:

One idea for my next one (if I ever get around to building it) is to have 65,280 bytes of 10ns RAM, only 256 bytes for I/O space, and no ROM in the actual memory map. The OS will have to be loaded into the fast SRAM before the main processor comes out of reset. With a couple of tricks, the address-decoding scheme is almost as simple and fast as the single-74ACT00 method above.

Please let me know if you decide to do this. I may be able to help, based on some of my experience and research.

Apologies if I strayed off-topic.

Cheerful regards, Mike

GARTHWILSON · Post by **GARTHWILSON** » Mon Feb 24, 2014 2:29 am

BigEd wrote:

Hi Garth, now that we have attachments, would you be so good as to scan that article?
I found the text, but not the diagrams:
http://www.edn.com/design/other/4341478 ... OS-devices

Here it is. I didn't have a scanner when I wrote the post above nearly ten years ago.

Quote:

Please let me know if you decide to do this. I may be able to help, based on some of my experience and research.

Thanks. What did you have in mind? Programmable logic? Things have changed in the last ten years, probably for all of us, and hopefully for the better. I wasn't exactly a 6502 beginner when I made my primary workbench computer in 1993, but I've learned a lot since then, thanks partly to the fine folks here. That computer has undergone quite a few improvements over the last 20+ years. For many of those years I was planning my next workbench computer to have more I/O (especially different expansion buses), more speed, more memory, etc., but as I gained experience with what I had on the workbench, I found ways to expand it, which breathed new life into it, and I began to see that the expansion buses and various things I thought I needed were not only unnecessary, but were getting so complex that I wouldn't live long enough to carry out my ideas. I'd still like to build another one, with an '816 and at least 4MB of RAM and pull a few tricks to see how fast I can get it to go. The push at the moment now is to do several new features for my website, some being major. At the moment, I temporarily have a second job, both jobs being enjoyable, and don't have enough time to do everything.

MichaelM · Post by **MichaelM** » Mon Feb 24, 2014 3:40 am

Very nice. Thanks for posting the drawings.

GARTHWILSON · Post by **GARTHWILSON** » Mon Mar 27, 2023 2:57 am

GARTHWILSON wrote:

Here it is. I didn't have a scanner when I wrote the post above nearly ten years ago.

Someone asked me about a resistor value and transistor identifier. A common 2N4401 transistor should be fine. For the resistor: 5V-3.6V-.6V=0.8V across the resistor. 10mA would be an appropriate current for charging a NiCd battery of 100mAH or a little more (I'm guessing at the AH rating of the little ones I've seen); so 0.8V/10mA=80Ω. 82Ω is a close standard value. 10mA for the transistor base current is way more than you need, but won't hurt anything. These numbers can be modified depending on the SRAM, the transistor, and the battery.

Darn. I just looked at Mouser, and found they no longer carry any of the NiCd batteries that used to be mounted on PC boards for memory back-up. Jameco shows one, but it's no longer available. There are other sizes, so if you want to use one of them, I'm sure we can help you find appropriate parts values for this circuit. Otherwise, it'll be a different chemistry, so we may need to modify the circuit, depending on the battery's data sheet. We can probably do that, too. I suppose it's mostly lithium-ion now, which doesn't have the memory effect that NiCd had, and probably also has a lower self-discharge rate.