Hi, all:
I'm new here and I'm working on the 6502 project now.
There's a problem confused me about 6502 reset.
The document from WDC shows that RESB signal must be held low for 2 clock cycles. Coz the signal of RESB is synchronized to the PHI2. Does it matter to release the RESB at positive edge or negative edge of PHI2.


Thanks.

You can release it anytime, without regard for where phase 2 is at the moment. Just make sure there has been time for the power supply to come up to spec. and the oscillator to stabilize, and make sure there have been enough clock cycles after that for the processor to initialize itself before you release the reset line. The RES\ input is a Schmitt-trigger input, and you can even just put an RC on it as long as you connect the capacitor from the reset pin to the ground pin with the connections as short as possible. (There's not a lot of hysteresis on the input.) See http://www.6502.org/forum/viewtopic.php?t=342&start=0 and go down to Tip of the day, #3. There are lots of other tips there too.

Hi, all:

Thanks for u help.
and this is the mail from WDC for reference.
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Hi,

Sorry for the delay in responding to you. Here is some information about RESB.

RESB is usually an asynchronous signal and can be changed in either half cycle.

As long as you have 2 full cycles you should be fine. So if you pull RESB low
on the negative edge you should release on the second negative edge.

Internally RESB is sampled when PH2 is high and latched when PH2 goes low. If
you change RESB when PHI2 goes high you will be changing when the internal
logic would be holding PH2 high internally if you are using the STP
instruction.

If you have a choice we would suggest that you change RESB on the positive edge of PHI2.
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