Is there a simple single chip solution for adding an 8-bit latch off of the 6502 buss? I know I could use a 65C22 but I'd like to use something smaller and in DIP package, like a 74HC373 or 74HC374. Looking at the 74HC373 and 74HC374 Datasheets, it seems I can't use just a chip select signal for either one of these, or can I? Anyone got a simple solution, please?

TIA. Cheerful regards, Mike

Either would work. The select line for the '373 would be positive logic (active high, instead of active low) though, and should have phase 2 brought in so it's not transparent before the input data is valid and stable. The select line for the '374 could be negative logic, and the data would get transferred at the end of phase 2 when "deselecting" (kind of a misnomer) produces the rising edge it needs. The '373 will get the data out a little sooner, not waiting until the end of the cycle.

Edit: The '374 might be the better choice, as the write data is not guaranteed to be there yet when phase 2 rises. Using the '373 might give little glitches.

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I would recommend the newer 74HC574 or 74HC573. Same function but all input pins are on one side and all output pins on the other. This should make it easier to do the routing or wiring for the IC.

As Garth said, a single chip select should be possible as long as it is "qualified" to represent data valid. However, since in your project a PIC generates the CS and the phase 0 clock, it should not be a problem to generate a qualified chip select.

For the 74HC573 data must be valid for a minimum of 15ns before and until at least 5ns after CS (CK pin) high. Data will appear on Q with a propagation delay of 15-47ns at rising edge of CS and will be latched on the falling edge.

For the 74HC574 data must be valid for a minimum of 20ns before the transition of CS (CK pin) from low to high occurs (setup time) and must remain valid until the transition is completed (0ns hold time). Data will be latched and appears on Q after a propagation delay of 20-57ns.

The OE pin should be tied low in both cases.

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Thanks, guys. You've confirmed that I can't use just my chip select signal, as is. Even if I were to use the A0..A7 address lines as the latch inputs, my chip select signal doesn't go high until well after the falling edge of ɸ2 and after the 6502 presents new address data for the next instruction cycle. Bummer! I really don't want to add another chip to qualify the chip select to ɸ2 and it would be challenging to do it in software in the PIC.

Just thought of something... It would be very easy to assign a polarity to each chip select output in my "decoder map". If I set the polarity to "active hi" for the chip select pin connected to the 74HC574 'CP' input, then I could use the A0..A7 address lines as inputs and latch them on the rising edge of the active hi chip select (about ~200-ns after address valid and about ~200-ns before ɸ2 rising edge). The 6502 software would only need to read an address in the page assigned to the 74HC574 to latch new output data. For example, if I wanted 1-of-N active lo 74HC574 outputs I would read address $FE, $FD, $FB, $F7, $EF, $DF, $BF, or $7F and I would read address $FF to turn off the active lo output.

Would this work?

Thanks for the help, guys. Regards, Mike

If you could program a 22V10 GAL device, you could handle the CS-RW-PHI2 control logic and the 8 bit data latch in one chip. You can still get Lattice 22V10's in DIP (although the price is going up) and I can program those. I cannot program the Atmel versions.

Daryl

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Now it sounds like you want to use this as a bank select for windowing into a larger memory map. If that's it, and you won't be accessing that window of the memory map in the same clock cycle anyway, then the A0...A7 could be anything, and provide 8 more address bits in this widow. Your first idea would be fine too. Just don't change the bank-select byte from code running in that window. If that's what you want to do though, I'd say it's '816 time, as the '816 does this and so many other things so much better.

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What's an additional VIA among friends, anyhow?

Hi Daryl,

I'd love to use a GAL but I'm concerned about being able to source the quantities that might be needed to kit a project.


Hi Garth,

Good guess but that's not it. I want to use the 74HC574 for eight /SS (slave select) outputs for an SPI interface. The PIC has a nice high speed multi-mode SPI module that I'd like to use to interface to a GPU (video & keyboard), an SD Card (for storage), and other devices.

Do you think my active hi chip select idea for the 74HC574 will work?

Mike

Er... make that 7, not 8. (You'll need a value where none of them are selected, right?) Make sure you look at our 65SIB spec which extends SPI in several directions at once. viewtopic.php?t=1064&start=105

Since the data will not get fed to the SPI's shift register in the same instruction that you set the select with, then yes, it will work, and the added delay (a portion of a clock cycle) will not be any problem-- if I understand your intentions correctly.

This part is so off-topic we might want to take it offline to discuss it, but I'll mention it here anyway. I was just working with the PIC's SSP in slave SPI mode for the first time (before has always been in master mode), and apparently there's no way to get its buffer-full bit to show the reception of more than one byte per SS\-low time, so I could not use SS\ to also indicate the start of a message. Instead, I had to select and de-select for each byte, and then have the slave determine where the end of one message and the beginning of the next is, based on what's in the bytes. Pretty mickey-mouse. Let me know if you know of a solution. I was using my 6502 workbench computer to send the data to it. (There's the 6502 content! )

If Lattice 22V10's might be discontinued anytime soon, perhaps it would be a good time to buy a lifetime supply if you think you'll want them.

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Reading from address $FF will set all 74HC574 outputs high.

I've seen it, thank you. Pretty slick!


I haven't done slave mode yet, though I will be very soon. Still, that just doesn't sound right. Is your slave sending a byte, even if it's only dummy data, for each SPI transaction? Anyway, please tell me which PIC you're using and I'll take a quick look at the Datasheet and see if there's an easy way to simulate something.

Ok, I'll get right on that (grin)...

Mike

I recommend the 74AC version if you are going to be using it to map memory. The HC devices are actually no faster than 74LS. 74AC also has better fanout.

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The Lattice GALs were discontinued several years ago. However, huge quantities of them were produced and can be gotten from a variety of sources.

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Have you thought of the possibility of just adding another 64Kx8bit (or maybe even 64Kx16bit) SRAM as address decoder? I've been thinking of this for my own project for a while...

That way, each address that gets generated from the 6502 gets "translated" to an 8-bit or 16-bit value; the extra memory is simply a huge lookup table.

Now... the problem is how to initialize that address lookup RAM...

===Jac

Ah yes, you're right.


16F72. The SSP is the same across many variations though. I think I tried sending dummy data (like CLRF SSPBUF), but I don't remember for sure. Whatever is in the shift register there whould get sent anyway, as the clock is controlled by the master, not the slave.


Comparing the numbers in my National Semiconductor books, the HC is usually faster than LS, but in some cases it's the other way around. It won't matter for SPI selects though.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

If it is for slave selects of an SPI interface there is another option. Have you ever looked at a 3 to 8 decoder chip?

The 74HC137 seems to be ideal as it has a latch with low strobe (GL) and decodes 3 bits into 8 with enable. So you could have $x0-$x7 selecting the slave and any of $x8-$xF disabling the slave select (A-C=A0-2, G2=A3, G1=1).

However, as with the 573 data must be valid for the whole duration of chip select but CS is now active low. A chip select to write a latch is not required to be active for the whole duration of PH2, but for any time inside the period where data is valid. So a short strobe generated by the PIC will do.

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Yes, I have thought about using RAM or Flash as a decoder to get past the 1-MHz limitation of my current design.

That, my friend, is a problem begging for a simple and elegant solution.