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Michael
PostPosted: Fri Jan 10, 2014 5:50 pm 
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Location: Michigan, USA
Greetings guys:

The R65C02 Datasheet I have says that it takes seven cycles after detecting the rising edge on the /RES pin before the CPU fetches the reset vector but I'm only counting five cycles. May I ask if anyone has tried this, please?

Thanks in advance. Cheerful regards, Mike


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Last edited by Michael on Fri Jan 10, 2014 6:33 pm, edited 1 time in total.
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GARTHWILSON
PostPosted: Fri Jan 10, 2014 6:13 pm 
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Fetching the vector is part of the 7-cycle reset sequence.  After that, it's off and running in your reset routine.

BTW, if you were to want a single cycle per byte fetched, you could use something like A9 (LDA#) instead of EA (NOP).  You'll get LDA #$A9 over and over which takes two cycles for a two-byte instruction.

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Michael
PostPosted: Fri Jan 10, 2014 9:18 pm 
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Thanks for the info'/confirmation, Garth. My interpretation of the Datasheet was way off.

I've never had a way to see those extra clock cycles before. Single cycle stepping, as well as having the ability to feed the R65C02 with data (after disabling the address decoder circuitry), is pretty cool...

Cheerful regards, Mike
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osolabs
PostPosted: Tue Oct 15, 2024 5:21 pm 
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It takes 7 cycles because a RESET is just a BRK command ordered via hardware.
T0 fetch brk opcode
T1 discarded data read cycle
T2 Push High byte stack pointer to Stack
T3 Push Low byte stack pointer to Stack
T4 Push Status register to Stack
T5 Fetch low order byte for RESET VECTOR FFFC
T6 Fetch High order byte for RESET VECTOR FFFD

you can see it in the 6502 schematic https://blog.espaciotec.com.ar/wp-conte ... /06/18.png

The Predecode logic inserts an OPCODE of 00 or BREAK when a reset is pushed.

Regards

Carlinho
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