GAL16V8
AIIEIDE1

/DEV    A0     A1     A2     A3     PHI0  /DDEV   nc     nc    GND
 RW    /OEW   /OER    ENW    ENR   /CS1   /CS0   /IOW   /IOR   VCC

;
; Generate the signals for the IO Registers which are
; C0x8 .. C0xF  Normal Access to the ATA Registers
; C0x0          Write only access to the ATA Data Register
; C0x7      Read back of the High-Byte Register
; C0x6          Read Write Access to the Alternate Status/Control Register
; C0x1          Read Write Access to the High-Byte of IDE Bus Data
;

IOR   =  DDEV   * /A3   *  A2   *  A1   * /A0   *  RW   ; C0x6
   +  DDEV   *  A3            *  RW   ; C0x8..F

IOW   =  DDEV   *  DEV   * /A3   * /A2   * /A1   * /A0   * /RW   ; C0x0
   +  DDEV   *  DEV   * /A3   *  A2   *  A1   * /A0   * /RW   ; C0x6
   +  DDEV   *  DEV   *  A3            * /RW   ; C0x8..F

CS1   =  DEV    * /A3   *  A2   *  A1   * /A0      ; C0x6

CS0   =  DEV   * /A3   * /A2   * /A1   * /A0   * /RW   ; C0x0
   +  DEV   *  A3               ; C0x8..F

ENR   =  DEV   * /A3   *  A2   *  A1   * /A0   *  RW   ; C0x6
   +  DEV   * /A3   *  A2   *  A1   *  A0   *  RW   ; C0X7
   +  DEV   *  A3            *  RW   ; C0x8..F

ENW   =  DEV   * /A3   * /A2   * /A1   *  A0   * /RW   ; C0x1

OER   =  DEV   * /A3   * /A2   * /A1   *  A0   *  RW   ; C0x1
   +  DEV   * /A3   *  A2   *  A1   *  A0   *  RW   ; C0x7

OEW   =  DDEV   * /A3   * /A2   * /A1   * /A0   * /RW   ; C0x0
   +  DDEV   * /A3   *  A2   *  A1   * /A0   * /RW   ; C0x6
   +  DDEV   * /A3   *  A2   *  A1   *  A0   *  RW   ; C0x7
   +  DDEV   *  A3            * /RW   ; C0x8..F

DESCRIPTION
/*

IOR   This is the ATA Interface IO Read Request Signal and is low only when
   IO-Registers C0x8 .. C0xF and C0x6 are read accessed
   
IOW   This is the ATA Interface IO Write Request Signal and is low when
   IO-Registers C0x8 .. C0xF and C0x6 are write accessed or when C0x0 is
   write accessed. Reading to C0x0 does not activate IOW. This is
   to avoid additional read cycles when writing to the ATA Dataregister
   this is required as the 6502 processor always reads the location
   before writing to it and some IDE Interfaces count the number of
   access rather than the number of write access when transferring a
   block of data from the Host to the Device.
   
CS0   This is the standard CS0 Select Signal of ATA Interface and is used to
   access the packet interface registers. This signal is asserted during
   write access to C0x0 and during any reference to C0x8 .. C0xF.

CS1   This is the standard CS1 Select Signal of ATA Interface and is used to
   access the alternate status or control register. This signal is
   asserted during access of addresses C0x8 .. C0xF.
   
OER   Output Enable of the Read High-Data Register. This is enabled when
   reading locations C0x1 and C0x7. When reading C0x7 the current value
   of the data high-byte register of the IDE interface is read back.
   When reading C0x1 the last value of high-byte read from the IDE bus
   is returned. Note that accessing C0x7 destroys the last value read
   from the IDE bus and is only used for debugging purpose.

OEW   Output Enable of the High-Byte Data Register to the ATA Device.
   This signal is asserted with every write access of the IDE bus.
   The high-byte data register must be set previously by writing the
   appropriate value to C0x1. This signal is also asserted when reading
   location C0x7 in order for the Read High-Data Register to read the
   current Write High-Data Register value for debugging purposes.

ENR   Enable Read High-Data Register Latch. Activated on each read cycle
   to the ATA Registers and when reading location C0x7 to fetch the
   previously store value of the high-byte data register.

ENW   Enable Write High-Data Register Latch. This is only asserted when
   writing to location C0x1 to set the high-byte data value which then
   is used on every write cycle to the IDE bus.

*/
END