Hi all,

Ok, I have what might seem like an odd timing question, but I'll do my best to explain.

I'm exploring a multi-speed clock circuit, similar to what d???? (can't remember his nick off hand) created for his 65816 project, but a bit different, and I was wondering about timing with regard to the 6522 and the CPU.

Let's say I permanently clock the '22 at 10 MHz

Let's say the CPU is adjustable clock for between 2.5 and 10 MHz (with only 2 speeds selectable, high and low, high would be the same speed as the '22, and low would either be 2.5MHz or 5 MHz)

Can I interface with the via at 10 MHz if the cpu is running at 5MHz, or do I have to make sure the CPU is running at the same speed as the via for any transactions between the cpu and the via?

I'm thinking I need them both running at the same speed, but I'm just not sure - if I can have them running at different speeds, then the solution is easy; if they need to run at the same speed, then the solution is more difficult and I may put off implementing it until I've experimented more.

-T

_________________
-Tony
KG4WFX

I can imagine doing it with extra hardware-- but if you already have the hardware to change the µP speed, wouldn't it be easier to just bump the speed up when you want to address the VIA? or is it that you have to go through the VIA bit to control the µP speed in the first place? Will you have more than one VIA? and if so, will they all be at 10MHz full time? If you don't need a timer in every VIA running consistently off the 10MHz clock, you may be able to have one VIA running at the µP's speed to have control over that speed. You can also keep a VIA T2 running at a consistent speed (regardless of bus speed) by having it clocked by PB6.

Another approach might be to use the VP signal to reset the clocking logic for the 65816 to 10MHz, as a "safe default" for touching hardware. Although always resetting it to 2.5MHz or 5MHz may be a nuisance, it at least gaurantees the CPU can talk to the VIA every time an interrupt occurs, thus guaranteeing rapid response.

Also, even if the VIA is used to control CPU speed, the VP signal ensures that a simple BRK instruction is all that's needed to bring the CPU back up to speed to access the VIA registers again.