Hi all,

I was wondering if anyone knew what the input impedance is of the PHI2 pin on a 65c22s? I've looked thru the datasheet and they talk about their test loading conditions as well as the internal bus holding capabilities, but I haven't seen anything about the clock input impedance anywhere.

_________________
-Tony
KG4WFX

At DC, it's essentially infinite, consisting of only the tiny leakage current that gets through the gates' insulation. This leakage is guaranteed to be no more than a microamp for input voltages between .8 and 2.4V. The datasheet doesn't say what the leakage is outside this range. I assume the idea is that if you can supply at least this amount of current, you can drive it to a valid logic state (at least at low speeds).

For AC, just consider it a capacitor of 5pF maximum. If you were feeding it sine waves, you could figure the capacitive reactance is 1/(2*pi*f*5pF), where f is the frequency in Hz. At 1MHz that would give you 32K ohms minimum. But the wave wouldn't be square without a lot of harmonic content where that number would be considerably lower, so you can't just go with a simple reactance number or say it's a 10K or a 32K input.

It gets a lot more complex when you take into account the inductance of the leads and possibly wire-wrap wire, the traces, transmission-line effects, and so on. That's where you start considering problems with ringing, ground bounce, and other things that leave the issue of impedance behind as a non-issue. When you get up into clock speeds where the impedance might be low enough to think about, the problem actually gets dwarfed by these other issues. IOW, you probably don't have any reason to worry about impedance.

Well, my consideration was multiple in effect, my question was wrong, but a the time I was trying to get out the door and I really didn't think it thru completely. I should have asked for input capacitance of the phi2 pin and not impedance.

At 1MHz it isn't a problem, heck at 4MHz everything was running perfectly.

At 8MHz (after fiddling and shifting clock signals so less and less were sharing the same buffer, it seemed to work better, although not reliably - looking at the scope, the square wave looked pretty bad considering the feeding square wave looked really good) and moreso at 10 MHz, I believe it starts to become a bit of one...

For example: I have 4 vias I want to run, they all need the clock signal; the cpu, glu chip, and inverter (inverter being used to clock my bank address chip per the 65816 datasheet) driven by a seperate buffer from the vias.

My clock signal is 10MHz. With knowing now that the input cap is 5pF, each one has a max cap react of ~1592, less when taking into account that the clock is a square wave and not sine.

Four of those connected to one clock signal makes a nice little parallel path, and now my input impedance is max ~398, much less when taking into account a square wave.

if the driver chip I choose is meant to drive a greater impedance then that, I could run into a problem of loading the driver chip down, and hence changing the characteristics of the square wave possibly making it un-useable. So I definitly need to be aware of that.

I'm trying to figure out how many vias I can safely run off of one buffer without causing a loading problem on the buffer.

Of course, I can also see how easy it would be for wirewrap to create a problem as well - especially with very long wires, and wires running over each other at higher speeds having a mutual inductance effect which it is possible that I am seeing the sum of that as well.

I like going thru things systematically and do my best to understand each potential problem and correct it if necessary.

That was the thought process I was originally going after.

Most of my little projects in the past have been much simpler, fewer IC's, fewer vias, smaller design area, slower speed, any time I needed a faster oscillator it was only used to run a PIC so the problems were very different from what I am seeing here. Well, I wanted to challenge myself; guess I came up with a design that is challenging me

_________________
-Tony
KG4WFX

My 1990 National (now Fairchild) book says the 74ACT04 has a maximum low-to-high (the worst) propagation delay of 8.5ns with a 50pF load at room temperature. (That includes output rise time.) 50pF would be a minimum of 10 VIA phase-2-input loads and probably more (15?) except it does not take into account your sockets and wires. For comparison, HCT's is 20ns, and LS's is 22ns. The LS spec is at only 15pF though, and I don't have the info on how much the heavier 50pF load would further slow the LS down to make an accurate comparison against the CMOS.

To get the maximum '816 operating speed, you might have to experiment with the 74ACT573's LE timing. The set-up and hold timing requirements in the book just don't jibe with WDC's timing data if you use their suggested circuit which Bill Mensch personally told me was not even tried at the higher speeds. (I know the off-the-shelf '816 can work up there though because one of WDC's customers was running it at 20MHz in a production product. Even though it's faster than WDC spec.s, they wouldn't be able to make money selling this product if the failure rate were substancial.)

That might be where some of the problem is - I just got a set of ACT's in on Friday (I had some 74ACT04's, but they all got used, I was limited to 7404's and I had a 74f04 and 74s04 laying around). The ACT's may solve my problem. Of course, it could also have something to do with the length and position of the wirewrap wires, and of course the sockets with the lengths of the leads could be throwing something else in the mix.

Currently I'm using ACT373's on the 816, is there a reason I should switch to 573's?..... Never mind, I jus found the 573 datasheet, and can already see why I should switch; I like having the inputs and outputs on opposite sides, I'll have to order some.

_________________
-Tony
KG4WFX