GARTHWILSON wrote:
I suspect there may be some systems where the ISR keeps feeding data to the UART transmitter and the RTS line only gets looked at by a non-ISR task, leading to its taking more bytes to stop the flow than the UART's buffer has. IOW, that even if the UART had an 8-byte buffer, it may take more than 8 bytes to come to a stop. Is anyone aware of such a system?
I'm not. The two UARTs with which I am familiar that have internal transmit FIFOs will indicate via a status register bit when the FIFO is full. In the case of the 26C92, it may be programmed so that it stops transmitting as soon as the receiving entity deasserts CTS, which is how I am using it in POC V1.1. The response time to CTS is sub-microsecond, which means transmission will be stopped well before the next start bit would be sent.
The buffer to which I am referring is the circular one maintained by the drivers in RAM.