I am comparing the instruction execution speed of different 8 bit microprocessors. One document gave the amount of t states and machine cycles. Another one gave out values under the label of cycles. Does cycles refer to machine cycles or instruction cycles?

That would depend on a number of factors, but most importantly on the processor. Further, I think that you need to define what you mean by machine cycle and instruction cycle.

For example, consider the 6502 processor. It is an 8 bit processor. It uses a two phase clock, and it performs one memory cycle per clock period. I would describe its machine cycle as a memory cycle because the bus is always performing a memory read or write operation, unless a wait state is requested.

On the other hand, consider the 8051 processor. It also is an 8 bit processor. It performs reads of program memory at a rate of 1 read every 6 cycles. However, if the instruction fetched does not require an operand, then instruction is executed during a second program memory read cycle of 6 clock cycles, but the data read from that program memory access cycle is discarded. The discarded byte from program memory is re-fetched during the subsequent 6 cycle program memory access cycle, and the process repeats.

If the instruction fetched in the first 6 cycles requires an operand, then the operand is fetched during the second 6 cycles. Execution of this two byte instruction fetched using 12 cycles can be overlapped with the fetch of the next opcode during the following 6 cycles.

Thus, although the first instruction was single byte, the execution required 12 cycles of the clock. The second instruction required 12 cycles to fetch the opcode and its operand, and 6 cycles to complete execution, or a total of 18 cycles. However, because the execution phase is overlapped with the instruction fetch of the next instruction, the effective number of clock for the second instruction is still 12 clock cycles. For the 8051, the basic execution cycle is 12 clock cycles, and for that processor it's known as a machine cycle.

The problem in comparing the 6502 and the 8051 is that they both have the same effective execution rate. The standard speed for the 6502 is 1 MHz, and it executes instructions at a rate which is a multiple of the memory access rate of 1 MHz. The standard speed for the 8052 is 12 MHz, and it executes instructions at a rate which is a multiple of 12 clock cycles, or 1 MHz. The internal logic of the 6502 is more complex and performs more operations per clock cycle. The internal logic of the 8051 is less complex and requires more clock cycles to perform the same functions that a 6502 performs in fewer cycles.

Generally I would provide more points to a processor that performs the same amount of work in less cycles. Higher operating speed generally means more power dissipation, so I would lean toward a lower power solution if possible.

_________________
Michael A.

Here is the page I was looking at. It is the 6800. https://www.jameco.com/Jameco/Products/ProdDS/43481.pdf

In the case of the 6800, it has the same type of memory cycle as the 6502. I would charactersize it as having a machine cycle which is equal to its memory cycle. For both the 6800 and 6502, I would characterize the instruction cycle as the number of the memory cycles required to complete the instruction.

In the matter of the 8051, the machine cycle is pretty much set as 12 cycles. Its instruction cycle is measure as multiples of these machine cycles.

A fair comparison of the these two very different processor architectures will make the comparison on the basis of the machine cycles. Both the 6502 and 6800 have similar implementations since the 6502 was designed by many of the same designers that designed the 6800. When compared in this manner, the 6800, 6502, 8051, and many other 8-bit processors from this era turn out to have similar instruction execution rates. The thing that really separates the 6502 from similar processors is its efficiency. Its instruction set and HW architecture provide some efficiencies that generally allow it to outperform other processor when both are compared on a "machine" cycle or memory cycle basis rather than a clock cycle basis.

If an internal clock generator was used to generate the higer clock, and that was never reported, then all the energy spent on these comparisons is simply a waste. Each of these processor has their pluses and minuses. The 6502 is simple and has very good interrupt response time because it doesn't need to save a lot of registers. Its math (ADC/SBC) is somewhat non-standard but it chains to multi-precision in a simple way while only using one instruction. The 8080/Z80 have far more instructions, but limited indirection capabilities. Their larger registers sets may be advantageous in some situations but require more cycles to save interrupts are required. They support multi-precision arithmetic but require multiple instructions to support it: ADD/ADC, SUB/SBB. Further, BCD arithmetic requires a separate adjustment instruction (probably because of a patent on flow-through BCD adjustment).

All in all, you can choose virtually any of these processors and easily meet most of your processing requirements. I personnally like the simpler memory cycle of the 6502/6800, but I have done far more programming with the 8080/Z80 and the 8051 than on the 6502 because that's what my customers were using. Consultants can always determine the processor that the must use in projects.

_________________
Michael A.

I presume that you mean can't there?

Since the Z80 has been mentioned, I'll point out that the Z80 takes something like three clock cycles to perform a memory access (if memory serves, referred to as an "M-cycle"), unless there are wait-states involved, and four cycles for an opcode fetch (an M0-cycle) because it also does something to support old-style DRAMs. Something about providing an 8-bit "refresh" address cycle after fetching the opcode. More fun and games include the limited indirection facilities (already mentioned), specifically only THREE indirect registers available. Assuming that an indirect memory access doesn't involve "prefix" instructions (a further 4-cycle delay), we're looking at 4+3=7 clock cycles for an 8-bit indirect register load. Compare with the 6502's zero-page indirect addressing, and you have 1+1+2+1=5 clock cycles for an 8-bit indirect load... And up to 128 indirect "registers". And the disparity only gets worse as you go into practical code. I know that the NES's (1.7 MHz 6502) win over the SEGA Master System (3.5 MHz Z80) was a triumph of licensing agreements more than anything else, and the SMS video hardware was a bit more capable than the NES, but the NES CPU ran rings around the SMS.

Sometimes, when comparing CPUs, the thing to look at is how long it takes to perform actual useful work rather than a memory access, or other operation. This will require working out instruction sequences for performing various operations, figuring out how many clock cycles it takes to execute the sequences, and then either assuming equivalent clock speeds or converting to some common unit of measure (such as picoseconds).

There's a similar topic at viewtopic.php?f=2&t=18&p=190#p190. (I'm not referencing the top of it, because it started out as something else and then migrated to a conversation about comparing the performance of different processors. It wouldn't be a bad idea to go a few posts above this one though.) There's some good material there so I won't repeat it here.

The Apple II actually did two memory accesses per clock, so at 1MHz, it did two million memory accesses per second, using the first half of each cycle for the video and the second half for the processor to access memory.

The fastest off-the-shelf 6502's top out at about six million instructions per second (6 MIPS), but there are ones inside custom ICs that are running over 200MHz, which is about 50 MIPS, the equivalent of about 100 MIPS on a non-extended PIC16 (if it's a job the PIC16 can do at all).

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?