This is my MARC-1 SBC.

With the PCB layout I started over three times. But I think I’ve got it right now.
It’s pretty simple in address decoding and features. Only an ACIA for I/O.

This is mainly for experimenting and interfacing with the breadboard and will replace my current prototype.

The ATtiny delivers a clock of 3,6864 MHz. This is divided to 1,8432 MHz. for the ACIA and 0,9216 MHz. for PHI2. With a jumper, PHI2 can also be set to 1,8432 MHz.

There are buttons for reset, CPU stop and single instruction.

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Marco

It looks like some vias are really close together. Did you run a design rule check ?

Hi Arlet,
I’ve used EAGLE’s default design rules, it only gives me some errors with drill sizes of the vias. Do you have any suggestions?

BTW. I used the technique you suggested to apply two polygon layers and assigned them to one level. Before there were 42 air wires, and after there were only 4 left.

Could I use smaller trace width’s for home etching, now I use 0.016”. and for power 0.024”?

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Marco

I was looking at these 3 vias in the middle. What's the space between them ?

Also, some vias can be easily avoided, like the two on the left, by letting the red trace go horizontal for a little bit.

It’s 0.01”. I made some room between them.

Can I reach the upper side for soldering on the sockets? If so, there could be a lot more vias omitted.

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Marco

Ah, I didn't think about the fact you were going to etch these yourself and don't have plated through hole. I don't know about sockets, but if you solder the IC in without a socket, it's much easier to reach the top side. For cheap ICs that may be a good option.

If you get some sockets now, you can practice soldering the top side on a piece of perfboard, and see if its possible. Or maybe somebody else has more experience with sockets and can tell if there are suitable ones that can be soldered on the top.

While etching my board, a topic showed up which just fits in here!
viewtopic.php?f=4&t=2760

Arlet, your new Sandbox design looks so clean and easy, I know it’s not...
I’m glad with your advice, it just pushed me over the edge. Here is a photo shoot of the results:


I use a technique described here:
http://thomaspfeifer.net/platinen_aetzen.htm
It’s in German, but I have some similar links in English.
http://www.riccibitti.com/pcb/pcb.htm
http://fullnet.com/~tomg/gooteepc.htm
http://www.dr-lex.be/hardware/tonertransfer.html

The paper I use is from an electronics catalog. I print the bottom layer normal and the top layer mirrored.


Then I glue those two sheets together with one side open like a pocket.

This way I can slide the double sided print in. For melting the toner onto the copper I use a hacked laminator. It regulates at a temperature of ca. 200 deg. Celsius. And heats at both sides simultaneously.

The vias I drill with 0,5mm. I keep the vias at open places to be able to solder a wire through it. Also when I can reach the upper side of the solder pad, I can use it as a via.

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Marco

There are over 100 vias and over 300 pads, so I'm occupied.


It has a fairly high success rate. The only flaws are when the copper isn’t clean enough or when the printer has little drop outs.

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Marco

Looks nice.

Looks amazing. I couldn't dream of doing a homemade PCB of that good a quality and have to get mine made in China. Looking forward to seeing the board all populated with parts.

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8 bit fun and games: https://www.aslak.net/

That's definitely the best home board-etching job I've ever seen.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks for the compliments!
However, soldering the true holes is more work than I thought.

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Marco

Phew, after some days I finished soldering. Unfortunately, Atmel decided to update their Atmel Studio, and my AVRISP-mkII Clone stopped working.

Here is a picture of the result. What’s not pretty is that the copper already begins to corrode.

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Marco

Nice looking board. Just use some Brasso on it and it'll stay shiny.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

BTW, I don't see a bypass capacitor near the EPROM. An EPROM generates a large transient when /OE is asserted.

Something else to consider is that fill planes (aka ground pours) are detrimental to high speed digital circuits.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!