Hello out there,
I think I have now the final draft of the address decoding for my MOUSE project, moving from the breadboard to a PCB.
The plan is to have 32k SRAM from 0x0000 to 0x7ffff and also 4 x 8k blocks for different use. Two blocks (0x8000 and 0xA000) can be used by external modules, 0xC000 is the I/O area with one RIOT, one VIA and two MC6850 ACIAs. The upper 8k block is mapped to the internal ROM. The pictures shows the underlaying logic, using only one quad 2-input NAND (one quarter as inverter) and one 74HC139 to decode the 4 8k blocks. By using the different chip-select inputs of the I/O devices no further logic seems to be needed. Here's the "masterplan":
Code:
0xxxxxxx xxxxxxxx 32k RAM 0x0000-0x7FFF
100xxxxx xxxxxxxx 8k external 0x8000-0x9FFF
101xxxxx xxxxxxxx 8k external 0xA000-0xBFFF
11000000 1RRRRRRR RIOT 0xC080-0xC09F (IRQ3)
11000001 0000RRRR VIA1 0xC100-0xC10F (IRQ2)
11000010 000000RR ACIA1 (6850) 0xC200-0xC203 (IRQ1)
11000100 000000RR ACIA2 (6850) 0xC400-0xC403 (IRQ0)
111xxxxx xxxxxxxx 8k ROM 0xE000-0xFFFF
x - don't care
R - register address line
RIOT : /CS2 -> I/O /CS, A7 -> CS1
VIA1 : /CS2 -> I/O /CS, A8 -> CS1
ACIA1: /CS2 -> I/O /CS, A9 -> CS0, +5V -> CS2
ACIA1: /CS2 -> I/O /CS, A10 -> CS0, +5V -> CS2
It would be great if somebody could take a look at this and tell me if I'm totally wrong or have missed something.
Thanks,
Mario.