I have a monitor command for my WDC65c02 that is called "quit" and is supposed to stop everything before I pull the plug (not necessary, but it feels less cruel and I can print a silly goodbye message). The first version used the STP instruction ($DB), based on the interrupt primer, which says that both the WDC65c816 and the WDC65c02 have it. And lo and behold, it assembled fine with Ophis (produces $DB as expected), and seemed to run on the prototype hardware (no more output, though I haven't checked any pins).

However, on the py65mon, the same code jumps all over the place, and direct assembly produces an error ("Syntax?"). I went back and checked the WDC Programming Manual, and it says that STP is a 65c816 instruction only, not the 65c02.

Obviously, something is not right here. Is this an undocumented function? I figure the way to solve this is to figure out if the 65c02 is actually doing what it is supposed with when it gets a $DB, or if it is just going off into nirvana. Maybe somebody has tested this already? I'm out of breadboard space at the moment .

The WDC W65C02S datasheet has the STP instruction with opcode $DB, so I would say it is a valid instruction. However, I have never used it.

Daryl

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I checked back in older data sheets to see if it had been added more recently (like late 90's for example). The earliest data sheet I have for the W65C02S is Aug '92, and even that one has the STP instruction. And, since it's in several places, I can be pretty confident it was not another oversight in WDC's data sheets.

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If I look at py65 code the STP opcode is not implemented but the WAI opcode is. I don't know, what py65 does with undefined opcodes, but I gues they are 1 byte NOPs.

https://github.com/mnaberez/py65/blob/m ... pu65c02.py

I would try and add NOP NOP JMP * (self) after the STP, so it works anyway.

One could argue that a STP is useless in a simulated environment, but in my emulator it is implemented and the monitor is invoked when the emulated CPU is stopped. So it acts more like a real BRK in that sense as it gives full control back to the debugging environment.

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Ah, okay. Thanks everybody for the help, I'll put it back in the code. Included is a screen shot of the Manual where there is an X missing for the 65c02, just for the record.

The copyright date of the Eyes & Liechty manual (at least my copy) is 1985. I wonder if none of the 65c02's had it yet at that time.

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What's an additional VIA among friends, anyhow?

The Rockwell 65C02 didn't have WAI or STP.

http://www.downloads.reactivemicro.com/ ... asheet.pdf

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Ah, is it worth sending WDC a line in cases like these? Can't be that hard to fix in a new version of the programming manual.

STP has existed in the 65C816 since inception (c. 1984). I believe STP first appeared in the WDC 65C02 when it was converted to a static core in the early 1990s.

You can verify that STP is functional by watching SYNC on the 65C02 or VPA on the 65C816 after issuing your QUIT command.

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Looks like the manual is provided "as is". Even the RMB, SMB, BBR and BBS instructions are only mentioned in Appendix C - "The Rockell 65C02". A WDC 65C02 seems not to exist for the programming manual. The 65SC02 is another story, but that one is not mentioned either.

You are always better off with the individiual hardware datasheet to see, which instructions are supported by the CPU. The programming manual then explains, what they do.

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Neither the original 65c02 nor the Rockwell R65c02 support WAI or STP. The W65c02 has the same instruction set as the R65c02 with the addition of WAI and STP.

I dunno if they'd be totally useless in an emulated environment. That environment would need to provide some sort of equivalent of interrupt signals to make them work as designed, though. WAI halts the processor until an IRQ is sensed, and STP until a RESET is sensed.

When any hardware interrupt is sensed, not just IRQ.

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