yzoer wrote:
I'm considering changing my board over from a z80 to a W65c02.
Welcome back from the dark side!
As noted by BDD, Bus Enable is an asynchronous signal. What this means is that, unlike the z80, the W65c02 has no bus arbitration circuitry on-chip.
You supply the hardware that manages the handover of the bus -- and suspends the CPU, using RDY. (Coupla gates & flip-flops... it's not that difficult. I expect it'd be a piece of cake with an FPGA.)
Quote:
Anyone know how the W65c02(s) let's you know when the bus has tristated?
To be clear, there's no
need to let you know. You can be sure the bus is tristated simply by negating BE then waiting a few nanoseconds. (For the exact figure, check tBV in the timing diagram.)
BigDumbDinosaur wrote:
Also note:
3.5 Memory Lock (MLB) [etc]
Needless detail, IMO. The vast majority of DMA applications (eg: straight-forward Input/Output from an ordinary peripheral device) can ignore MLB, and also SYNC/VPA/VDA. An exception would be if the other device sharing the bus were another processor,
and the two processors required a system of shared semaphores in memory.
cheers
Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html