You're right, of course.

Formally, a crowbar circuit is present to protect the load, not the power source. However, electric railroad traction electricians/technicians use "crowbar" to describe the abrupt breaking of a circuit in the face of any fault. A lot of my time in the 1970s and 1980s was involved with Diesel-electric locomotive and subway car control systems, so old terminology habits tend to die hard.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

Just gotta heat sink it so if exposed to a direct short, the 7805 doesn't convert itself from a semiconductor to a full-time conductor.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The 7805 does have a thermal shutdown and short circuit protection, so under normal circumstances it should survive.

More info on crowbars (and an actual circuit) are found here: http://en.wikipedia.org/wiki/Crowbar_(circuit)

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It isn't cheating. Sometimes you just need to have a working example in hand to get your thoughts marshaled on what you want to do. Everything that we build is modeled in some way on prior art. My large scale model locomotive came about because I had access to the full-sized version and hence had detailed knowledge about what goes on inside it.


It's actually not that difficult to lay out a PCB. There are some basic "rules" that can be followed that generally make layout relatively painless. As I noted elsewhere, there's a sort of feng shui to it that become apparent with experience. Again, studying something that has been made and works will give you the needed clues.

Although I have a lot of experience with PCB layout, stretching back some 25 years, I had never laid out a computer PCB prior to designing POC V1.0. Having looked at plenty of them over the years, I wasn't totally at sea on how to proceed. You can do the same. All you need is some confidence and a modicum of understanding and common sense—not to mention plenty of advice from 6502.org members like me who think they know-it-all.


See attached picture. It's a device called PLCC chip extractor that is available through many electronics parts sources. The one I linked is the one I have—I purchased it in 1990 and it's still going strong.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

That's what I used to think until one day I accidentally applied a short to a 7812 on a gadget I was fooling with. It didn't have a heat sink and it failed before I realized there was a problem. It didn't smell very good.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

The LM340T-5.0 is nearly the same thing, but definitely has current limiting, SOA protection, and thermal overload protection, and I've seen it turn itself on and on very rapidly in an overcurrent situation. As it was getting too hot, it would shut itself down to protect itself, the die temperature would drop to where it could operate safely again so it would turn itself back on, then start getting too hot again, and repeat the cycle a couple dozen times a second or more.

The LM317T (which takes a couple of resistors to set the output voltage) is another one I would recommend if a linear regulator with 1.7V drop-out is ok.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Also, the "grill mark" it burns into your finger is quite painful!

Power supply discussions really bring up the heat!

Actually I have a bench power supply from the 80’s, it just needs some kind of display to read the voltage and amperage. But it works without it of course.

That’s not bad, for a more permanent supply I would use this schematic from a commercial product.





Tempting /O\

I have found one!

well, I’m almost done... 8-P.
I think I’ll start with the data and address lines. Any suggestions?

_________________
Marco

What is that large IC in the top right ? Maybe you want to bring that down so that the bus wires can go straight.

Starting with data/address is a good plan, but keep in mind that you may discover that some parts need to be moved, so don't try to make it really nice and beautiful at first. Also, feel free to skip a few if they are regular anyway. So, you could do D0, D1, D4, D6, D7 at first, and fill in the rest later when the placement is finalized.

I also recommend making a ground plane on top and bottom, and start by trying to route your signals on bottom layer. Many folks advocate using a power plane, but for 2 layer boards, I recommend sticking with 2 ground planes, and some fat power traces. The reason is that your signals are going to chop up your ground plane, and if you only have one, you'll end up with a bunch of broken pieces. If you have two ground planes, and a bunch of vias connecting them, they'll work together as one solid plane.

Also, make sure you run a DRC (design rule check) on a regular basis. If you have your boards made professionally, check if you supplier has a .dru file for Eagle that checks against their exact manufacturing capabilities. By doing a DRC in early stages, you avoid having to redo a bunch of work later.

Thanks for the help!
This one will be two layer homemade PCB with use of a laser printer and laminator.
That large IC is the SID
The limitation is that I have to make the through holes by hand. I’ll choose free areas for the vias and start traces at the bottom layer of the IC’s. (I hope that makes sense?)

For a possible next and more complex design I’ll choose 4 layer.

I checked that supplier, and it really looks promising.

_________________
Marco

If you're etching it yourself, a DRC is still a good idea. You can fill in values that you feel comfortable with, and then check that you don't have any shorts, or wires too close together.

For a professionally made board with 6 mil trace/clearance and small vias, you can do an awful lot in 2 layers. It's just a bit more work.

Edit: one of the things you can do with 6 mil is route 3 signal wires between two pins at .1" distance, assuming the pads aren't too big.
Here's an example from my 6502 sandbox board. All signals from the socket are routed on top layer. Of course, they're going into an FPGA, which allows arbitrary pin swaps, so that helps a lot. The bottom layer only has ground, bypass caps, and a fat power trace. Also note plenty of vias connecting top/bottom ground layers.

Amazing, I won’t even ask what one can do with your 6502 sandbox board.

Although, could you give me a comparison how much “logic ports” go into an XC9572XL CPLD and in a Spartan 3?

With some reassurance from Daryl, I managed to complete a tool chain and it’s finally working! I’m just beginning to explore the 9572.

_________________
Marco

It's probably close to a factor of 100 between a lower end FPGA and a decent CPLD.

When I have some more time, I'd like to make a new revision of the sandbox board, but with a twist: I want to have the 6502, SRAM and FPGA all on the same bus. This sacrifices some flexibility, but frees up a lot of FPGA pins. The FPGA will then become a super peripheral, capable of supporting video, sound, SPI, GPIO, USB, timers, UART, Flash, and whatever else I'd like. Using the BE pin, the FPGA can take over the bus, and pre-init SRAM, perform DMA, and generate video.