Hi all. I am writing an emulator for a theoretical processor I am designing for fun and learning, and I am basing it heavily off of the 6502 (registers, addressing, instructions, etc.) and I am currently working on interrupts. I basically need to learn all there is to know about interrupts. I understand the concept, but the thing I don't get is how an interrupt is triggered and how that would be emulated. I am also wondering if/what data comes along with an interrupt, if no data comes along with an interrupt and multiple devices are causing interrupts, how do i know which one is causing the interrupt?

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thanks. I'll be back here if I need any further help!

Most of your questions can be answered if you use a little diligence with a search engine. That said, you should give Garth Wilson's interrupt primer a good read. It goes into quite a bit of detail on 6502 interrupt processing.

Also, please stop by the "introduce yourself" topic and tell us a bit about yourself and what you are trying to accomplish.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Oops! You posted just as I was posting.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

So, as far as the processor design goes... instead of having the interrupt vector stored in a memory address (which would be hardcoded...) would it be a bad idea to have a register for it? Can't see why that would be a bad thing really..

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

So, the difference between IRQ and NMI is that NMI takes precedence over IRQ yes?

For my CPU design, would it be a good/bad/either way idea to do something like this:

IRQ₁
IRQ₂
IRQ₃

etc.. for some fixed number and basically have multiple interrupt handlers and pins to trigger them? If I did this, well.. I would have to figure out how to determine what happend first, I would prefer to just execute them in the order they come in though..

The important difference is that an NMI can't be ignored. An IRQ can be ignored by setting the I (interrupt disable) bit in the status register. I recommend you read up on and fully understand the 6502 architecture before attempting to emulate/simulate a 6502. In my opinion, you're putting the cart before the horse right now, as your questions indicate that you lack the knowledge needed to accomplish your goal.

Incidentally, if an IRQ and NMI simultaneously hit ("simultaneously" meaning during the same instruction processing cycle) the 65xx family will acknowledge NMI first.


Prioritizing interrupts is usually a chore handled by a programmable interrupt controller. Most MPUs have only a few hardware interrupt inputs, IRQB being the most used one on a 6502. External hardware and/or software polling must be used to differentiate interrupt sources.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

As far as NMI being serviced even if I is set, I remember reading that but I forget to type it, but yeah. As far as removing polling, that's not really my intention.. It's really just for more functionality, but I would only have 2 or 3 or something like that... As far as prioritization, I would probably do what you said Garth and serve them based on priority.. And correct me if im "wrong" but the best way to do that would be to have sort of queue which would hold the requested interrupts and then whenever the clock ticks just serve any irq requests in the queue?

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Also, there may be more interrupt sources than there are interrupt inputs. The PCI bus in a PC is a perfect example of this. It has four possible interrupts labeled A-D. However, quite a few PC motherboards that supported only PCI had five or (in rare cases) six slots. So some software polling was still required to isolate and service an interrupt. It's a case of balancing the expense of more hardware against the "expense" of a more complex ISR.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Also one fine point regarding "priority" is that if an NMI handler runs a CLI instruction, that allows IRQs to interrupt it. I use this in some background processing scenarios on the C64, where a timer on the NMI starts a task, but IRQ display interrupts can still continue operating.

So there really isn't any priority aside from "simultaneous" triggering and the interrupt disable flag, which is set by the hardware when interrupted by either IRQ or NMI.

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WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

If you have more than one or two interrupt sources, it's better to have a vectored interrupt controller, where every interrupt source (or group of them) has a different vector pointing to its own handler. Modern microcontrollers have dozens of different interrupt vectors with great flexibility in priorities. For instance check out datasheet of a PIC32: http://ww1.microchip.com/downloads/en/D ... 61156H.pdf with 52 interrupt vectors, and 76 interrupt sources, each with their own priority setting that the programmer can change.

Of course, this is much harder to implement if your peripherals are external to the chip, but you'll be implementing your design in an FPGA, so it's natural to implement the peripherals inside the FPGA as well, and then it's not that hard to add multiple interrupt vectors and priorities.