enso:
The answer is that it goes very much along the lines described in the Xilinx app notes. I did not do the actual work, but I did commission it. Although you will probably want to use the serial port, our in-system Platform Flash reprogramming module uses an Ethernet interface also contained within the Xilinx Virtex 5 FPGA. I am not able at this time to release the source code (or a netlist) for this function, and it would not likely be of much use to you since it's in VHDL.
I think that you are coming at this from the CHOCHI FPGA board perspective, because you have used a Xilinx Platform Flash for that design. For my 6502 board using a Spartan 3A XC3S50A/XC3S200A device, I have chosen to use the SPI programming mode. Although the Xilinx Platform Flash is very simple to use and it is JTAG reprogrammable, my FPGA team and I have chosen a different path for any future designs.
There are two reasons for this course change. First, Xilinx has informed me the further development of the Platform Flash product line is not a priority. It is not their intent to terminate the production using existing fabrication lines, but like the case with the Spartan II family, if a fab change is required, then support for whatever products are being manufactured by that fab that can't be easily ported to another fab will simply cease to be produced after a last-time-buy notice is given.
Second, there's a substantial amount of complexity associated with using the BSCAN_SPARTAN component to program the Platform Flash from within the FPGA. First, there's a set of FPGA pins, not its own JTAG pins, that must be reserved and connected to the Platform Flash's JTAG pins. Second, the app notes simplify the problem by allowing only one device in the JTAG chain. Thus, on the CHOCHI FPGA board, there is a need to have separate JTAG chains for the FPGA and the Platform Flash.
(Sorry, still haven't soldered the connectors onto the CHOCHI board you sent me, so I can't say if you have one or two JTAG chains designed into the board. From the connectors that you sent, I would venture a guess that you put the Platform Flash and the FPGA on a single JTAG chain. This would mean you'd have to take the data in the app notes, and extend it account for the two devices on the chain.)
For my team's purposes, we wanted a path to higher density parts, and since Xilinx has issued that warning to us regarding its Platform Flash product line, my team and I have chosen to follow the third party SPI Serial Flash path recommended by Xilinx. On my Spartan 3A 65C02 FPGA Development board, I chose to use SPI configuration devices. It's is fairly straight forward to use these devices with all Xilinx FPGAs since at least the Spartan 3A family.
I can't say anything definitive regarding the compatibility of the various third party SPI serial Flash devices with the Spartan 3 and Spartan 3E FPGA families. I have not built any projects using either of these two families. I have recently brought up a Spartan 6 design and a Spartan 3A design using SPI serial Flash devices. And my FPGA team is using 256Mb devices for our new XC5VLX110T FPGA designs. In fact, both of us are using these type of devices for configuration and general storage.
On final thought on the SPI serial Flash configuration approach. Although it requires that the Xilinx tool download a custom image in the FPGA that contains both a BSCAN_XXXXXX and an SPI Master interface, the usage of this special programmer is transparent to the user. It also works in a system with several devices on the same JTAG chain. On my 65C02 FPGA board, I have an FPGA and a CPLD in the same JTAG chain, and I have not issues whatsoever loading the SPI programmer in the FPGA.
This custom SPI serial Flash programmer is supplied by Xilinx and supports a number of different SPI serial device formats. It's like choosing between the old Atmel small block Flash EPROM programming algorithms or the Intel/AMD large block programming algorithms. Luckily, there are a large number of parts from multiple vendors which are compatible, and much less expensive than the corresponding Xilinx Platform Flash device.
Finally, the pins that you use to connect the SPI Flash are general purpose FPGA IO pins. This is unlike the JTAG pins or several of the Slave/Master Serial configuration pins. Thus, with SPI configuration, you can use an SPI Master of your design, and one to which you can attach other peripheral devices without reserving additional FPGA IO pins.
If you still want to proceed on this path, I will try and provide as much help as I can. You'll have to give me a couple of days to get the data as I will have to consult with the designer.
Again, if you have any changes to make to the CHOCHI FPGA board, I would very much recommend changing from Platform Flash to an SPI Flash for the reasons I wrote about above.
_________________ Michael A.
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