nyef wrote:
Okay, how about having some way to modify the next instruction in the stream by ORing (or XORing) in some bitmask?
Cool suggestion, nyef! The
Apollo Guidance Computer used a feature like this, although I'm having trouble finding the doc I read years ago. Edit: see below
The feature in question used addition, not ORing or XORing, but the intent was similar. Prior to execution, but subsequent to being fetched from memory, an instruction could be modified by adding a value computed at run time. It was a sanitized version of self-modifying code. IIRC the original intent was simply to implement indexed addressing. The addition was expected to modify an Address Field located in the bottom of the instruction word.
That's clever in itself, but a fascinating quirk yielded capabilities far beyond what had been originally planned. Someone realized that an addition could also or alternatively modify the Opcode Field in the
top of the instruction word. Moreover, such an addition would produce an n+1 bit result -- a carry. This anomaly was recognized as an opportunity.
The carry was decoded along with the original opcode bits, and the opcode space was thus doubled. A whole new set of instructions could then be defined -- instructions which were only available via this curious back door technique!
Edit: In
this post on anycpu.org,
BigEd wrote:
The search term you may need is "extracode" - see page 15 and page 26 of
http://authors.library.caltech.edu/5456 ... e/1704.pdf
and other places.
Quote:
We therefore introduce a 16th bit called an extracode bit, which, when appended to the 3-bit op-code and set to 1, provides us with twice the number of instructions, giving us 16 op-codes. The extracode bit is set by an "Extend" instruction
and is reset by any instruction other than an "index" instruction.
cheers
Jeff
_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html