Since I am on a roll with crazy ideas, here is another one.

Arlet's core extended to 9 bits (FPGA BRAMs support 9,18 and 36). 9 bit data bus (nice for 3-bit-per-component RGB among other things). 18 bit address bus - 256K RAM. 9 bit constants and a 512-byte zero page.

The 18-bit processor is scaled similarly...

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

And reads from external RAM will have MSB set to 0 ?

No, 9-bit RAM throughout. A full 9-bit processor.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Hmmm.. Somehow not a phrase that rolls off the tongue, is it!

Also, I get a grin because it reminds me of the farcical band in "This Is Spinal Tap," who had specially-made guitar amplifiers that went up to eleven! http://en.wikipedia.org/wiki/Up_to_eleven

Seriously, though, I can see some appeal to the idea. It's cheap in terms of FPGA resources, and it gives you:

• twice as much zero-page space (always a precious resource, and a desirable location for I/O devices).
• twice as much stack space (partly making up for the lack of a full-width SP)
• four times as much program/data space (18 bit addresses)
• increased integer precision
• twice as much opcode space -- room for new instructions, or a new mode applicable to existing instructions. If you hit on the right idea, this could be pretty radical!

Do you anticipate using external RAM and/or external EEPROM? If so, you might be forced to go to 12 or 16 bits wide -- implying that some bits would be unused. If that happened, you might wanna revisit the decision to use only 9 bits in the core.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I'd immensely enjoy seeing the completed product. Please don't forget to implement
the stack from &001000 to &001777, and the reset vector at &777774!!

Mike

Indeed. Octal notation is a natural consequence.

I don't know why this goofiness is so damn attractive. 18 bit bytes are pretty nice however. Reminds me of Chuck Moore's processors that packed 3 6-bit instructions into each 'byte'. 18 bits is plenty for many applications. 65org18 Forth is something I'd like to see.

I haven't had a chance to look at the assembler for 'org16. I wonder how much work it would be to convert it to 18.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Thanks, Doc! I was very excited when I thought of this, for some reason.

I am a proud owner of a number of 18x256K SRAM chips. Needless to say I am itching to put them to use, along with the 700ANs, large enough for 9 or 18-bit cores...

The 700s have quite a few BRAMS as well, more than enough for the boot ROM etc.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

What do you have in mind doing about 8-bit I/O ICs?


I think it's ANS that says the word size has to be 16 bits minimum, next step 32 bits, then 64 IIRC-- no 18, 20, 24, etc.. Although ANS brought in a lot of good things, it also brought in things I don't like, in an effort to be too portable, sometimes at the expense of preventing particular hardware from performing its best. Fortunately it's not law. Going from 16 to 18 bits opens things up quite a bit. My first experience with Forth was on a machine with a 4-bit data bus and a 20-bit address bus, meaning it had a 1-meganybble address space (512KB), and it required five memory locations to hold a cell. It worked fine, and the 20-bit cells obviously gave a little more headroom than 16. That headroom would be just enough sometimes. For most of what I do, 16 is fine, but there are times that it's not quite enough, even though I may not need 32 bits with 64-bit intermediate results.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

You can always use the low 8 bits for IO data... What ICs do you have in mind? I imagine most magic will happen inside the FPGA anyway.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

I'm thinking of 6522 VIAs. Polling for interrupts normally involves first doing a BIT VIA_IFR instruction (which does not involve any registers except P) to check bit 7 of the 6522's interrupt flag register, and then you BPL or BMI. But if bit 8 (not bit 7) goes into the N flag, I suppose you could BVC or BVS based on bit 7 after a BIT instruction. (After it is determined that the particular VIA was the one that interrupted, next would be to determine which source in the particular VIA was responsible, if in fact you have more than one of the sources enabled. It is common that only one interrupt on a particular VIA would be enabled though, and in that case there's no need to further test to see which one it was, because you already know which one you enabled.)

In all the talk about FPGAs though, the I/O is something I find missing. The 6522 is much more than just I/O bits, having the timers with several modes of operation, a synchroous-serial port also with several modes of operation, handshaking, and seven interrupt sources including selectable positive or negative active edge.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

In an FPGA it's easy to configure the I/O to exactly what you need for a project. Unless you're porting existing code written for a 6522, there's no need to emulate one. Instead, it's easier to create a serial port when you need it, I/O pins when you need it, and a timer when you need it. And when you make a timer, you can make it exactly as you need it, perhaps with only one mode of operation, but 32 bits wide.

For example, the UART I made for my FPGA board only supports 8 bits, no parity, and a fixed baudrate. I have no need for other options, so why make things more complex and take up more resources ?

For the 9 bit CPU I would think that BIT checks bits 7 and 8, and that the peripherals put useful polling flags in those locations.

That's fine for the HDL enthusiasts, but not if you want to make a processor that others will use. My dream for all these stepped-up 65-family processors is that standard versions will be sold that one can plug in like a commercial processor and use without knowing any HDL or having any jtag programming capability or other special tools.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

On enso's board people can already use a serial port or I/O pins without knowing any HDL. If somebody is interested in the board, really needs a timer or something else, and doesn't want to deal with HDL, somebody can probably help out and make it available.

The 65org10: 1kB zero page, 1kB stack. 20 bit addressing.

If one were to use 32 bit RAM one could fit 10 bits into it as three bytes and have a couple of bits to spare for parity.
The cpu would have to do read-modify-write cycles to update the memory though, and some memory addressing magic would have to happen. It's interesting because a multiplier is probably needed to calculate the addresses.

Using three nine bit bytes 2^27 (128 MB) bytes of memory could be addressed. Triple byte addressing is used on the '816. How about support for the 'long' addressing modes in the 65org09 ?

Go nuts with the peripherals. Nine bit versions of them would be interesting. Some of the peripherals were constrained in their design because of the need to fit into specific pin packaging. there's fewer constraints in an FPGA. A nine bit version of an ACIA is easy enough to make, and incompatible with everything.

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http://www.finitron.ca

On the topic of peripherals and the standard nature of the 6522 VIA, there are open-source HDL versions of the chip, so it should be straightforward to construct something in-FPGA but having a conventional programming model. It's a good point that timers are handy.

See for example http://www.mike-stirling.com/retro-fpga ... gn-detail/ which takes its 6522 model from fpgaarcade.com

Cheers
Ed