Hi,

I searched everything in Google search, but I am not finding what I was looking for. The gate logic can only list AND, OR, XOR, NAND, NOR, XNOR, NOT, and BUFFER gates. I want to find "pass gate" as described tri-state or switch. There is no name as pass gate. If you talk about transistors, it does mention "pass transistor gate logic" or "pass gate" for short.

I attempt to redraw transistors in my schematic. It is easier to label some transistors as three or four characters as AND, OR, NOT, NAND, etc instead of drawing gate symbols.

Let's talk about accumulator register as we discussed in another threads couple months ago. The accumulator bit 0 register has three transistors (two inverters and one pass gate). I want to group two transistors into one box so that I can label "BUF". Third transistor is for clock 2 switch. I can label it as "AND" gate. The "AND" gate can only have one transistor as only one direction path from first inverter to second inverter. The "AND" gate's two inputs can be a0 and cclk and one output can be a0. It is easier to understand when you look at "AND" gate label in the box. It is the same as pass gate.

Can I label "AND"? Or should I label "PASS"?

The special bus has bidirectional path. It is not a good idea to label the transistor as "AND" because "AND" gate's input and output can't have bidirectional path. I can label "PASS" instead. What do you think?

Take care,
Bryan Parkoff

As you say, there are a few - perhaps just 16 - transistors on the 6502 which are genuinely bidirectional and will need to be modelled as such. Unless you cheat and modify the circuit - if you detect the direction that information must flow you can probably replace the pass gates with logic gates or a pair of back-to-back tristate drivers. In fact it's difficult to prove that all the other transistors are unidirectional: it's sometimes either a circuit-level property or a property of the surrounding logic.

I think we've discussed before how to approach the handling of recirculating pass gates and input mux gates.

Cheers
Ed

Hi Ed,

I am not aware I had discussed about input mux gate. We already discussed about recirculating. I agree with you it is difficult to model the number of transistors into gate logic or gate symbols. When I want to convert them into simulator project with C++ programming. The Boolean functions can be used. Sometimes, one transistor may need two or more gate logic or gate symbols.

I think you are going to agree that "AND" gate can be used on SBAC and cclk when I want to use recirculating pass gate.

Take care,
Bryan Parkoff

Hi Bryan
I had a quick look, and this conversation seems to be on a similar topic:
viewtopic.php?p=25648#p25648

Cheers
Ed

Hi Ed,

Yes, I remembered as we discussed D latch. I did read threads twice yesterday for a review purpose. It does not sound like D latch has input mux gate. I will analyze the logic and research D latch later.

Take care,
Bryan Parkoff

Ah, well it's possible we haven't discussed! (By the way, I'm a visual person, so I pretty much need a picture or diagram to follow. Even a link to visual6502 would help, for any specific circuit - for example http://visual6502.org/JSSim/expert.html ... dpc23_SBAC)

Can you similate them something like a 4066 bilateral switch? The 4066 itself would be much too slow in real hardware, but gives the idea.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi,

I created S/R latch formula in Microsoft Excel. Microsoft Excel warns me from using circular reference, but I chose to enable circular reference. Of course, iteration will slow your computer, but it can limit 100 times while you modify values in "Set" cell and "Reset" cell. Everything works well. That is why I am able to write simulator project.

I am trying to implement two inverters and two pass gates into D latch. The performance is not an issue when you want simulator instead of emulator.

I am not sure I understand your comment like 4066 bilateral switch. Please clarify.

Take care,
Bryan Parkoff

Indeed, the 4066 works like a collection of pass gates
http://ist.uwaterloo.ca/~schepers/MJK/4066.html
But there's still the question of how to model them.
Iteration is one approach - visual6502 iterates - but that costs you some performance.

Hi,

We already discussed SBAC and a0 register in previous threads.

Take care,
Bryan Parkoff

Hi,

I spent my time thinking about D latch. A big question is that how can a0's node 737 hold value 1 while cclk's t1507 is disconnected or turned off. I am sure value 1 will be changed to value 0 in a0's node 737 unless cclk must be raised immediately to avoid losing data.

Is this D latch really dynamic storage? If yes, the number of transistors are always reduced from complex.

As you suggested to model mux gate, node 146, special bus' node 54, cclk, and sbac are connected to mux's four inputs and a0's node 737 is connected to mux's output. The two switches of sbac and cclk can be performed very quickly in order to keep data from losing due to delayed time.

I want to add. I thought you might be interested to study nMOS transistors. Here is the link.

http://www.scribd.com/doc/39789947/CMOSunit3-5notes-Premananda-PUNITHGOWDA-M-B

Take care,
Bryan Parkoff

Yes, for sure, a node like 737 is a dynamic node and will store charge for a couple of milliseconds. It will certainly be necessary to model the storage - but not necessary to model the leakage.