BigEd wrote:
It may be that a pair of NAND or NOR gates is a safer implementation of a D-latch, but there are very few D-latches like that on 6502. Is the aim to model what we have or to model what we'd prefer to have?
We are agreed that it is undesirable to have both SBAC high and Phi2 high is a problem. The question is how to model it, or whether to model it. The 6502 doesn't do that (I think) because the control lines are conditioned elsewhere, upstream of the drivers. If the circumstance doesn't arise, there's no need to model it, unless you specifically want a general and encapsulated model of the D-latch as implemented. In which case, I suggest you model as '0 wins'
You are quite right that the very widespread idiom of using dynamic charge storage as the basis for latches and flip-flops has a problem with charge leakage. That happens on a timescale of milliseconds, whereas normal operation is on a timescale of nanoseconds to microseconds. So again in practice there's no need to model this. If you really wanted to model it you could, at the cost of complexity and with a verification problem.
The point of a model is to leave out the unnecessary details!
Hi,
I spent my time thinking about D latch. A big question is that how can a0's node 737 hold value 1 while cclk's t1507 is disconnected or turned off. I am sure value 1 will be changed to value 0 in a0's node 737 unless cclk must be raised immediately to avoid losing data.
Is this D latch really dynamic storage? If yes, the number of transistors are always reduced from complex.
As you suggested to model mux gate, node 146, special bus' node 54, cclk, and sbac are connected to mux's four inputs and a0's node 737 is connected to mux's output. The two switches of sbac and cclk can be performed very quickly in order to keep data from losing due to delayed time.
I want to add. I thought you might be interested to study nMOS transistors. Here is the link.
http://www.scribd.com/doc/39789947/CMOSunit3-5notes-Premananda-PUNITHGOWDA-M-BTake care,
Bryan Parkoff