IIRC the SID's RNG was based off the internal white noise generator...
Anyway, in my case the problem with a PRNG is that the values are always the same after power up.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502

You could take a simple PRNG, like a LFSR, and add an external input signal to mix in some independent noise. For instance, the CPU could read a bunch of uninitialized RAM, and write the bits to the PRNG input. You could also add a simple white noise generator, like this one

Try a different search engine, or different search term. I typed white noise generator "8-pin" into ixquick.com which works the same as google but doesn't have the moral, political, and privacy issues, and the first result was for making one with at PIC12F675. The next two were about the National Semi MM5837 8-pin IC.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

OT - thanks for pointing to ixquick (and startpage.com). I truly despise g**gle and the complete disregard for privacy exhibited by businesses (and am amazed at people's lack of outrage). ixquick seems to be a lot better than duckduckgo.com.

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In theory, there is no difference between theory and practice. In practice, there is. ...Jan van de Snepscheut

Or it could be that neither of these is actually, you know, random. They're pseudo random. Not even clear that they don't start up with the same sequence, they very well may. Audible white noise doesn't have the requirements of actually being random, we humans aren't that discerning.

One is simply a PRNG in a PIC. Another example (neither of these) I saw repeated every 6 hours.

So, yea, these don't really count.

Actually, I wanted to implement my design in a CPLD, but the Xilinx tool would always minimize the circuit, since it had no input, so I never managed to get it working. Would anyone know how to implement that design of mine into a cpld or fpga, and get the logic blocks to recreate that same design?

I also chose to do this circuit for the collage project, because there were no discrete RND chips, so I didn't work on something that existed in abundance, like what my professor initially suggester(enhanced full adder).

To be fair, google reports the same page as the first result when you use that same search query.

By the way, there are some techniques to get a real random generator on an FPGA. See for instance: http://teal.gmu.edu/courses/ECE646/proj ... 7/RN-1.pdf‎

Note that you'll have to fight the synthesis tools to get these properly implemented and not optimized away.

That is the problem, I tried to fight it, but it still didn't work.

Found a good app note from Maxim Integrated that explains a few things of interest, and it's a simple design that they do measurements on up to 100MHz although it is from 2005.

So maybe better products are available to improve the design for a lower operating voltage (i.e. 3.3V) and @ higher frequencies?

The AN says the higher voltage Zener diodes (14V+) work better than the lower voltage Zener diodes. Also the lower bias current (@10mA) was just as good as the higher current (@60mA). So maybe some simple voltage doublers, like on Garth's primer would be in order and we could have a working 3.3v circuit.

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65Org16:https://github.com/ElEctric-EyE/verilog-6502