As a collage project I've built a random generator circuit of my own, and implemented it in tsmc 0.18 um topology, and made simulations in LT spice(which took forever on my pc).
I even built a prototype using only 4000 series IC, and it works.
The idea was using a pair of oscillators made out of inverters, but with extra xor gates that could invert the oscillators phase at any moment, and what I did is to take the output of one oscillator and use it to invert the phase of the next, and then I made such a ring of four of those, and had two such pairs. The end result got xor-ed, and fed into a sorta LFSR for a few cycles, and the output then is latched to a 8 bit latch. The 4000 series prototype could generate 12000 bytes per sec @5V and 24k @12V. The chip simulation was much faster.
I've made a schematic in Eagle later, but it is hopeless to try to fit the circuit on the board, even the auto router can't figure it out.
I've included the original documentation(you will need to use google translate if you want to read it, I didn't translate it yet) and the eagle files.
I did get a good grade for this project, but I've never tested the thing properly with the random testing algorithms, but I see no reason why it shouldn't pass them.
Edit: I've made the circuit interface so that it would nicely fit on the 68/65xx bus(or any other cpu bus).