Thanks for the pointer to the paper - there's a version at
http://www.inf.fu-berlin.de/lehre/WS94/RA/RISC-9.html which is more legible for text (but not for the images). It's a pity that ARM wasn't on their radar.
I'll concede the LDM/STM. I think the delayed branches is a red herring - which is to say, in my view it's not an interesting critical property. I accept that I'm deviating from Patterson and that he coined the term and started the revolution!
As for number of addressing modes not being one, I think that might be a red herring. The important point here, in my view, is that there should not be any expensive addressing modes - for example, indirect modes.
The crucially practical points would, in my view, be:
- cheap implementation should be possible
- enough additional clock speed from the simple implementation to compensate for the lack of complex instructions
- easy compiler target
(As we both know, high-performance implementations become complex and are not cheap: the crucial point is that a simple implementation is sufficiently performant.)
Cheers
Ed