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PostPosted: Wed Jul 31, 2013 3:09 am 
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I found this http://searle.hostei.com/grant/z80/SimpleZ80.html#Interfacing today, and it is so simple!

Sadly, its for a z80 :cry:

Does anyone have anything this simple laying around for a 6502 computer?

See, I'm not so interested in the hardware aspect as I am the software. I have both 65c02 and z80, but I've never written z80 code.
In other words, I want a project I can get working on a breadboard over the weekend that will allow me to connect a serial port to an
old monitor and get started on some code.

I'm working on a 6502 operating system at the moment.

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PostPosted: Wed Jul 31, 2013 4:21 am 
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You could do it with very little change using the last diagram on the clock-generation page of the 6502 primer to get the RD\ and WR\ signals, and you'll need something in the address-decoding department. And have you looked at the circuit potpourri page of the primer?

Using 65c22 VIAs for I/O gives a lot more flexibility than the diagram on Grant's page though, because individual bits of the VIA can be programmed to be inputs or outputs (and changeable on the fly, allowing open-drain equivalent arrangements too), have parallel handshaking, a synchronous-serial port to use with gobs of shift registers, seven interrupt sources, timer/counters, and certain bits can be tied to the timer/counters for additional flexibility. The outputs of Rockwell and WDC VIAs are very, very strong, and the inputs of the WDC VIA's inputs are truly high-impedance. You can get a given amount of I/O with less construction work too. It really is a better way than all the latches on that page.

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PostPosted: Wed Jul 31, 2013 3:58 pm 
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GARTHWILSON wrote:
Using 65c22 VIAs for I/O gives a lot more flexibility...outputs of Rockwell and WDC VIAs are very, very strong, and the inputs of the WDC VIA's inputs are truly high-impedance.

Just a reminder that WDC's 65C22 comes in two flavors: the W65C22N, which has current limiters and an open-drain IRQ output; and the W65C22S, which has no current limiters and a totem-pole IRQ output. The latter is recommended for new designs.

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PostPosted: Wed Jul 31, 2013 7:32 pm 
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Grant's UK101 design is nearby:
http://searle.hostei.com/grant/uk101/uk101.html

The chip count is a little higher than the Z80 design. In part, that's the complex decoding (lack of a separate I/O space) and in part it's the choice of dividing the UART clock. For smaller chip count, you'd simplify the memory map, use a clock can, and choose a clock frequency which gives a standard baud rate. That is, something more like his minimal 6809 design: http://searle.hostei.com/grant/6809/Simple6809.html

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PostPosted: Thu Aug 01, 2013 12:15 am 
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Yeah, I've been emailing Grant lately. He is going to upload a more simple 6502 example soon at my request. Really awesome guy.

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PostPosted: Fri Aug 09, 2013 4:34 pm 
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Grant updated his site: http://searle.hostei.com/grant/6502/Simple6502.html

Pretty nifty to see such a small circuit. I think it really helps out the newbies to learn the basics when you only have 7 or 8 ICs to deal with. I will be attempting this as my first 6502 SBC. I'm hoping to learn the concepts enough to come up with my own designs.

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PostPosted: Fri Aug 09, 2013 5:43 pm 
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That's about as compact a circuit as you can build and still have a functioning computer. However, it may be possible to make it just a teensy bit more compact:

  1. Use a can oscillator running at 1.8432 MHz in place of the crystal circuit. Along with this change, use a 2 MHz 65C02 (or better yet, a W65C02S), not an NMOS part. If you must use an MPU that can't run at 1.8432 MHz, retain U8 to divide the clock.

  2. Connect U3's /IRQ output to IRQ on the MPU, disconnect IRQ on the MPU from Vcc and connect to R4. Of course, an interrupt service routine to process data inflow will be needed with this change, as well as a buffer, but that's not a big deal (Garth describes the procedure in detail in his interrupt primer) and is the price you pay to reduce the chip count. :D

  3. Ground T1IN on the MAX-232. A succinct ISR will clear a waiting byte from the 6850 faster than the next one can be sent, even at 115.2 Kbps. Therefore, TIA-232 flow control shouldn't be required. Of course, you could run the 6850 at a slower rate to assure that an overrun doesn't occur.

  4. Remove U7.

If the above changes include an MPU capable of running at 2 MHz or higher, U8 won't be required and the total chip count will be six—assuming you don't consider the can oscillator to be a chip.

Notes:

  1. It will probably be necessary to press the reset push button after power on, as the MPU's /RES input will instantly jump to Vcc, thus failing to satisfy the time that /RES should be low following power application and the start-up of the clock. A simple series connected R-C circuit between /RES and ground will introduce some needed delay.

  2. If this circuit is built with a W65C02S (recommended over the NMOS 6502 or a Rockwell part) the RDY pin on the MPU should be pulled up to Vcc through a 3.3K resistor, not directly connected to Vcc. The circuit as designed can result in damage to W65C02S if a WAI instruction is accidentally executed.

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PostPosted: Fri Aug 09, 2013 6:02 pm 
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BigDumbDinosaur wrote:
  1. It will probably be necessary to press the reset push button after power on, as the MPU's /RES input will instantly jump to Vcc, thus failing to satisfy the time that /RES should be low following power application and the start-up of the clock. A simple series connected R-C circuit between /RES and ground will introduce some needed delay.

Yes, I would expect only trouble from the reset circuit as drawn there. At least some of the 65c02 brands had hysteresis on the reset input so you could just use an RC there, but WDC doesn't specify anything about hysteresis, so it might still be best to use a Schmitt-trigger gate to feed the reset input, as I show on the reset page of the 6502 primer.

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PostPosted: Fri Aug 09, 2013 6:09 pm 
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The circuit at http://wilsonminesco.com/6502primer/pot ... ml#BAS_CPU has 6 ICs, including the crystal can oscillator and a Schmitt-trigger reset circuit. It has the 6522 VIA instead of the 6551 (or other) ACIA, but you could have both, or add several of each with no further circuitry for address decoding. The circuit gives 32K of ROM and 16K of RAM.

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PostPosted: Fri Aug 09, 2013 8:54 pm 
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GARTHWILSON wrote:
BigDumbDinosaur wrote:
  1. It will probably be necessary to press the reset push button after power on, as the MPU's /RES input will instantly jump to Vcc, thus failing to satisfy the time that /RES should be low following power application and the start-up of the clock. A simple series connected R-C circuit between /RES and ground will introduce some needed delay.

Yes, I would expect only trouble from the reset circuit as drawn there. At least some of the 65c02 brands had hysteresis on the reset input so you could just use an RC there, but WDC doesn't specify anything about hysteresis, so it might still be best to use a Schmitt-trigger gate to feed the reset input, as I show on the reset page of the 6502 primer.

I seem to recall from somewhere that the W65C02S would satisfactorily function with a simple R-C delay on the RESB input. That said, a Maxim (Dallas) DS1813 econo-reset could be used instead of the Schmitt-trigger IC, which would count as a chip.

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PostPosted: Fri Aug 09, 2013 10:07 pm 
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I just wrote this and I guess I clicked on the wrong thing and it went up in smoke. Fortunately it was short. We'll see if two of them show up now.

BigDumbDinosaur wrote:
I seem to recall from somewhere that the W65C02S would satisfactorily function with a simple R-C delay on the RESB input.

Sounds good. I'll look for it.

Quote:
That said, a Maxim (Dallas) DS1813 econo-reset could be used instead of the Schmitt-trigger IC, which would count as a chip.

I didn't mean that another IC should be added for the Schmitt-trigger gate. The basic whole-computer circuit at the top of the potpourri page uses an otherwise unused section of the quad NAND which, for this reason, we make a 74xx132 instead of a '00. The DS1813 in a TO-92 (or smaller) would however save space because it replaces a few discretes.

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PostPosted: Fri Aug 09, 2013 10:18 pm 
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The whole reason I wanted to go with this setup is because it was simple :)

I'm actually getting to the point to where I'm losing interest in the hardware details. At least when it comes to designing my own computer. Like I've always said, I just want something to run software on. If I could afford an older computer like an Apple ][ I would just get one :)

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PostPosted: Sat Aug 10, 2013 4:50 am 
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Johnny Starr wrote:
The whole reason I wanted to go with this setup is because it was simple :)

I'm actually getting to the point to where I'm losing interest in the hardware details. At least when it comes to designing my own computer. Like I've always said, I just want something to run software on. If I could afford an older computer like an Apple ][ I would just get one :)


C64 can be cheap, and a C128 lets you scratch two itches -- 6502 and Z80. Problem would be shipping, I think.

Have you thought about simply working against a simulator while saving for a real machine?

Apple simulator would be best (if interested in one replicating an actual machine, vs simply a 6502) I would think since both the C64 and Atari had pretty specific keyboards. The Apples is pretty generic in contrast.

The Z80 simulator and CP/M archives are really good. Just maximize your terminal window and crank the font size up :). No different than the real thing.


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PostPosted: Sat Aug 17, 2013 2:07 pm 
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Thanks for the comments on my design and pages.

Yeah, agree with modifications mentioned above - all can be done if neded.

The interface could be interrupt driven, and I have done this for the Z80 design (buffered serial - code on my Z80 page) and I have also done it (but not published it yet) for the 6809 design.
The existing 6502 circuitry, when using the crystal has spare gates so the current design allowed a simple yet effective hardware control run purely from the 6850.
Regarding grounding T1IN if interrupt driven - this won't work because BASIC won't be ready to handle each character. After a very short time the input buffer would get full, so the buffered design that would be used (and is used on the Z80) raises RTS over a certain threshold then lowers it again at a lower buffer count.

The 6809 interrupt/buffer code is based on the same mechanism for the Z80 design, and the 6502 would also be the same.

However, if using the crystal and 74LS04 then there's no need for the interrupt option.

Anyway, time permitting, I'll upload interrupt-driven versions for both the 6809 and 6502 designs.

Any questions, please feel free to contact me.

Minimal 6809: http://searle.hostei.com/grant/6809/Simple6809.html
Minimal 6502: http://searle.hostei.com/grant/6502/Simple6502.html
Minimal Z80: http://searle.hostei.com/grant/z80/SimpleZ80.html
Minimal CP/M: http://searle.hostei.com/grant/cpm/index.html

By the way, all sourcecode for the 6502 version is now uploaded and online.

Grant.
http://searle.hostei.com/grant/


Last edited by zx80nut on Sat Aug 17, 2013 7:35 pm, edited 1 time in total.

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PostPosted: Sat Aug 17, 2013 4:21 pm 
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I think that me and Garth(or somebody else??) discussed a minimal 6502 system a while ago.
We came to the conclusion that you would need only few chips: 6502 CPU, RIOT chip, ROM chip, and a 74ls04 inverter chip.


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