Anyone just have one of those days?

I'm having one now. Can't figure out what is wrong, don't see the problem, logic analyzer is showing my funny data that isn't there (ie: it's showing storing $DD in a memory location, but I know it saw $00 on the LDA instruction), but everything seems to be proceeding normally, I've also now seem to have found an endless loop, but not sure why it's endless.....

Well, just venting. should be an interesting project if I can get passed the initial stumbling blocks

_________________
-Tony
KG4WFX

Some days it just isn't worth chewing through the restraints. 8^)=

I've seen problems like this and most have been caused by either timing violations or glitches.

Timing problems like data or address lines changing before WE and/or CE have been negated, data or address lines not stable for long enough before/after WE or CE. Logic analysers can give false results as their timing requirements are often not the same as the device you're trying to get working. I had this problem getting the network card to work on my Vic 20, the analyser said everything was fine.

Glitches can be harder to track down. Again with the Vic 20 there were problems with the expansion RAM I built. There are two R/W lines available on the Vic expansion port, one from the CPU and one from the VIC chip. Close inspection revealed that the one I had chosen was actually slightly shorter than Ø2 during write cycles and this caused a narrow (<10ns) read state either end of a write cycle. Enough to make it not work.

I've found the best way to deal with things like this, assuming code will run, is to write a short loop that toggles some pin to trigger my scope and then performs the action I want to test. This method was also used to produce some of the waveforms on my website.

Cheers,

Lee.