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PostPosted: Sun Jul 28, 2013 3:07 pm 
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Hello all,

I'm fairly inexperienced at working with hardware, and am trying to make a 6502 system to experiment with. I started by trying to put together a free-running 6502 by hard-wiring the data bus to $EA, with the idea that I could test it by checking the phi2 and address pins with my multimeter on frequency-counter mode, but couldn't seem to get a stable output (and rarely any output). Then I got an oscilloscope, and decided to start with just an oscillator based around some of the parts that I had used for the free-run system, on a separate breadboard... And I managed to get what appears to be a stable circuit, but it doesn't seem to do what I want.

My scope is a used Tektronics 2465 300MHz four-channel model, my one probe is an Elenco 1x / 10x 65MHz device, I'm using half of a 74HC132 for inverters and have wired the remaining inputs on the device to the positive voltage supply (because I read somewhere that letting CMOS device inputs float can lead to problems). The crystal that I'm using has been kicking around since I bought it something like ten-fifteen years ago (give or take), and is marked "ILSI", "3.579545", and "97 03". The package that the crystal came in is marked "CY3.57", "3.579545 MHz/HC18 Case", "CRYSTALS", and is also marked "jim-pak". I have been unsuccessful in finding a data sheet for the crystal at this time.

What I'm seeing on the scope is a period of somewhere between 70 and 80 nanoseconds, a slow rise time curve, and a bit of overshoot on the fall time. It took a bit to realize that the half-volt peak-to-peak that I was seeing was, in fact, five volts thanks to having my probe in the 10x position. My multimeter in freqency counter mode is showing a frequency of 14.2 MHz. From what I can tell, for a 3.579545 MHz frequency, my output period should be about 279 nanoseconds.

I'm willing to chalk the poor wave shape up to the high frequency, the use of a solderless breadboard, a possibly poorly compensated probe, the scope trigger and vertical being set to DC coupling (I have no idea if this is an appropriate setting for what I'm doing), the scope bandwidth being so much faster than the probe bandwidth, and not knowing what I'm doing. The oscillation frequency, however, is clearly a design or implementation fault, almost certainly a design fault.

At this point, I'm taking a two-pronged approach to trying to get this circuit to behave the way that I want. One is to read and try to understand Fairchild Application Note 340 (HCMOS Crystal Oscillators). The other is to ask for assistance here. Is my overall approach correct? Where am I going wrong? How should I know where I'm going wrong? What are the next things that I should try?

A diagram of my current circuit should be attached. It is loosely based on part of the whole-computer schematic (and clock source instructions) from http://wilsonminesco.com/6502primer/potpourri.html.

Thank you for your time and attention,

-- Alastair Bridgewater


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PostPosted: Sun Jul 28, 2013 3:57 pm 
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The solderless breadboard might be a problem, with its stray inductance and capacitance everywhere. Solderless breadboards are great for audio and low-frequency stuff, but not suitable for this kind of work.

Also, for anything beyond audio frequencies, the 'scope probe should always be in the x10 position. When it says it's a 40MHz probe or 100MHz probe or whatever, that's always in the x10 position. The spec. on the x1 position, if there is any spec. at all, never goes past a couple of MHz.

The resistor value you have across the crystal appears to be based on TTL or LSTTL. HCMOS has virtually no input current (only a teensy bit of leakage), so it biasing requirements are minimal. The one in the circuit you mention is 220K, not 220 or 230 ohms.

I know from experience that using Schmitt-trigger inverters with crystals can have strange effects like you're talking about too. As I mentioned in the clock generation chapter of the 6502 primer, understanding and designing good oscillators is beyond most of us, so using a crystal oscillator can is normally best for reliability under all operating conditions, board space, and labor, and the whole oscillator doesn't cost much more than a bare crystal.

Hopefully I didn't mess up on anything here. I just have a minute and I have to leave, so I'll look again at it later.

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PostPosted: Sun Jul 28, 2013 4:31 pm 
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Thank you, thank you, thank you. You're right, I did mis-read the notes for your schematic, and switching out the 230-ohm resistor for a 330K-ohm resistor (because that's what I had in stock and easily to hand) resulted in an oscillation period of about 280 nanoseconds, which is spot-on for what I wanted. The frequency counter reads 3.577 MHz, which is a touch high, but at the precision limit of its display.

I have been using my probe in the x10 setting, I remembered that as being important, just not precisely why. My confusion there was over the output on the scope. Once I knew what I was looking at, it wasn't a problem anymore.

The waveform shape is better, good-looking rise and fall, about two volts of overshoot on the fall, a little more on the rise, and a lot of ringing but, as you say, solderless breadboards aren't right for what I'm doing, and there's also the Schmitt trigger inputs to consider. Plus the lack of a bypass capacitor probably doesn't help. Setting the 20 MHz bandwidth limit on the scope shows no overshoot on the fall and a lot of... ripple? ringing? whatever, a wave shape on the high edge. At this point I'm going to see if I have anything suitable for use as a bypass capacitor to see if that helps, and then rebuild my free-run circuit.

Thank you again.

-- Alastair Bridgewater


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PostPosted: Sun Jul 28, 2013 7:54 pm 
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A bit of a follow-up:

I rebuilt my 6502 free-run circuit around the '132 oscillator, and it worked (I was temporarily worried about the A0 line frequency being a quarter of the phi0 line frequency, but once I worked out what the actual line states would be over four cycles then I was happy with it), but if I use the phi1 line of the CPU (a WDC 65c02 ordered from Mouser about a month or so ago) then the oscillator works but the address lines don't behave right. Is this likely to be from using a 330K resistor to bias the inverter in the CPU instead of a 220K, or should I chalk it up to a general problem with running an oscillator around a recent WDC CPU?

-- Alastair Bridgewater


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PostPosted: Sun Jul 28, 2013 8:07 pm 
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WDC no longer tests or guarantees the timings of the phase-2-in to phase-1-out to phase-2-out, but the circuitry is still there and I suspect will work as before even though they would prefer you use a totally external oscillator. However, I have not seen the onboard oscillator used with a crystal at more than a MHz or two regardless of brand or year, and you're going for nearly twice that. If you want crystal control of the frequency, there may not be any reliable way to get it at 3.7MHz with the onboard oscillator.

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PostPosted: Sun Jul 28, 2013 8:21 pm 
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GARTHWILSON wrote:
WDC no longer tests or guarantees the timings of the phase-2-in to phase-1-out to phase-2-out, but the circuitry is still there and I suspect will work as before even though they would prefer you use a totally external oscillator. However, I have not seen the onboard oscillator used with a crystal at more than a MHz or two regardless of brand or year, and you're going for nearly twice that. If you want crystal control of the frequency, there may not be any reliable way to get it at 3.7MHz with the onboard oscillator.

I concur with Garth. The least problematic way to get a reliable clock signal is by using a standard can oscillator. Only two components are required: the oscillator proper and a decoupling capacitor to dampen its switching transients at Vcc and ground.

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PostPosted: Tue Jul 30, 2013 3:14 am 
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I too am in need of a 3.579545 MHz oscillator, would it be OK to replace the 74132 with 7414 in the OP's circuit?


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PostPosted: Tue Jul 30, 2013 3:38 am 
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Where you're using the '132 as just a Schmitt-trigger inverter (by tying one input to Vdd), then yes, a '14 would come out to be the same thing. I do hope you're not using just TTL though! The 74HC would probably be a good choice.

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PostPosted: Tue Jul 30, 2013 6:46 am 
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BigDumbDinosaur wrote:
The least problematic way to get a reliable clock signal is by using a standard can oscillator. Only two components are required: the oscillator proper and a decoupling capacitor to dampen its switching transients at Vcc and ground.

Actually, four components for best results. The oscillator's output should be run through a 74AC74 (or 74ABT74) flop to produce a very sharp output with dead nuts symmetry. The WDC MPUs should be driven by a clock source that doesn't exceed 5ns rise/fall time.

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PostPosted: Tue Jul 30, 2013 2:34 pm 
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I actually have some 74HC04 chips on order that I'm planning to try with this. The only reason I'm using a Schmitt-trigger setup in the first place is because one of the gates is for the reset circuit for my CPU, and as I was trying to set up a free-run I didn't need the address decoding, and thus I had spare gates available.

On the other hand, the address decoding scheme that I'm looking at calls for at least four NAND gates and two inverters, so I might just end up using two '132 chips anyway.

Okay, the 7474 halves the clock rate, but can you then do something on the flipside, such as run a second 65c02 or other logic (DRAM refresh?) in the /Q phase? And if we're not supposed to be using the PHI1 or PHI2O pins on the WDC 65c02 do we then have to delay the PHI2 signal going to the 6522 and any other peripherals that need it (and if we generate separate /RD and /WR for interfacing other chips, the PHI2 signal being delivered there), and how should we go about it? I note that the w65c22 datasheet also says something about a 5ns rise time for PHI2...

And, while we're on the topic of oscillators, there's a pretty sinusoid at the output of the first inverter in my circuit. Having a quadrature sinusoid from that could be fun and useful.

-- Alastair Bridgewater


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PostPosted: Tue Jul 30, 2013 5:02 pm 
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nyef wrote:
Okay, the 7474 halves the clock rate, but can you then do something on the flipside, such as run a second 65c02 or other logic (DRAM refresh?) in the /Q phase?

Nothing is stopping you from using the /Q output as a Ø1 signal. It will be exactly 180 degrees out of phase with Ø2. An example of where such a signal would be useful would be in a bank address latch circuit for the 65C816. You could also use it to gate the MPU's RWB output so it doesn't go low (write) unless Ø1 is also low, which means that Ø2 is high, which in turn means that the data bus is valid.

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And if we're not supposed to be using the PHI1 or PHI2O pins on the WDC 65c02 do we then have to delay the PHI2 signal going to the 6522 and any other peripherals that need it (and if we generate separate /RD and /WR for interfacing other chips, the PHI2 signal being delivered there), and how should we go about it?

Connect the clock input of the 65C22 directly to Ø2—no signal delay is required or desirable. Also note that the 65C22 chip selects must be valid before Ø2 goes high. Don't make the mistake of qualifying chip selects with Ø2.

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PostPosted: Tue Jul 30, 2013 5:46 pm 
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Quote:
And if we're not supposed to be using the PHI1 or PHI2O pins on the WDC 65c02

I hadn't caught that before. BDD brought to my attention that they weren't testing or guaranteeing the delays anymore, but I missed when they changed their tune to also use phase2-in for everything, similar to the 65816, instead of phase2-out. The fact that other manufacturers have called phase2-in phase0 undoubtedly had part in why I missed it. Now I wish I had the means to experiment easily and move the timing forward and back, even on both edges, to find out what works best, evidenced by the highest operational frequency. WDC's data sheets have always had a lot of errors, but fortunately they always err on the side of being very conservative, ie, the timing margins, output currents, etc. are much better than they let on.

To reiterate what BDD said though, the 6522's chip selects must not be qualified by phase 2. It has its own phase-2 input, and the chip selects and R/W\ must be valid and stable a specified amount of time before phase 2 rises.

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PostPosted: Tue Jul 30, 2013 6:17 pm 
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Ah, the 6522 latches on the rising edge of PHI2. That makes a bit more sense, but now that I'm looking at the timing diagram for the 6502 I'm a little more worried about trying to run something on the "back side" of a clock cycle. I'll have to work out quite when the 6502 is driving the bus and when it's expecting the bus to be driven before I can do anything in terms of doubling-up that way.


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PostPosted: Tue Jul 30, 2013 6:20 pm 
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I wondered if BDD was overcooking things to include a divider to guarantee a 50% duty cycle. A check of a random can oscillator shows that it is spec'd at 45%-55% duty cycle. For some purposes that will be good enough, and for others it won't. In effect it knocks 10% off your frequency margin.

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PostPosted: Tue Jul 30, 2013 7:04 pm 
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Quote:
I'm a little more worried about trying to run something on the "back side" of a clock cycle. I'll have to work out quite when the 6502 is driving the bus and when it's expecting the bus to be driven before I can do anything in terms of doubling-up that way.

I don't know what you're thinking of running, but you might be interested in the topic The secret, hidden, transparent 6502 DMA channel. The first link there is unavailable at the moment (hopefully not permanently), but IIRC, it was about using an EPROM to tell which cycles of any given instruction are dead bus cycles so you can use those cycles for something else without slowing down the processor at all, and you can use the whole cycle, not just the phase-2-low time. You do have to contend with the fact that it won't always be the same for a given instruction, based on whether you're in decimal mode or a page boundary is being crossed in a branch or indexing; but the 65816 has VDA and VPA outputs, making that unnecessary. I just re-read the topic (very quickly-- more like "scanned").

Quote:
I wondered if BDD was overcooking things to include a divider to guarantee a 50% duty cycle. A check of a random can oscillator shows that it is spec'd at 45%-55% duty cycle. For some purposes that will be good enough, and for others it won't. In effect it knocks 10% off your frequency margin.

Another reason I said I wish I had the means to experiment easily and move the timing forward and back, even on both edges, to find out what works best, is that I suspect that there's more margin on one side than the other, ie, that the very best duty cycle won't be exactly 50%-- it's just that without knowing exactly what it is, 50% is the safest bet.

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