> I would have to disagree with this (if you were referring to the 'one cycle' part of of #2). I believe
> 'instruction cycle' should be what matters - after all, the physical clock pulse is just a technicality.
> The chip could (and some do) utilize a slow-ticking external clock and multiply it internally instead
> (like e.g. the MIPS R4000 which is normally called a RISC processor). Or even multiply or divide it into
> different frequencies for different sections of the internals. How the clock pulse relates to the
> instruction cycle varies a lot between chips, which for example means that you can't directly
> compare the clock frequency of a Z80 with the clock frequency of the 6502 when comparing how
> much the CPU can do per cycle (an old battle..
)
>
> -Tor
AFAIK the R4000 (and other processors) multiply the clock frequency internally because it is a problem to maintain signal integrity of high speed clocks along PCB traces. So therefore externally the clock frequency is halved.
Even if you consider PIC16 to not violate RISC trait #2, it still violates RISC trait #4 because the implementations require two clocks for a branch. There is no design feature to hide branch penalties.
To use fuzzy logic terminology, the set of "RISC processors" is not a crisp set; it is more of a fuzzy set with various degrees of membership. Some processors are very RISC, and some are barely RISC.
My personal taxonomy of RISC processors is:
Very RISC: MIPS, Alpha, M88K
Mostly RISC: SPARC, AM29K, PowerPC
Somewhat RISC: PIC16
Barely RISC: ARM AArch32
Toshi