I have posted the preliminary datasheet of my first programmable logic design. I call it the FTS1001, and I have designated all FTS10xx parts to be discrete 65xx(x) support chips. The FTS1001, obviously, is the first.

You can read it here: http://www.falvotech.com/datasheets/fts1001.pdf

Once again, it's a preliminary datasheet. There are many things relating to the design which have yet to be determined. I won't be able to determine them, in fact, until I have a working piece of silicon. This might not happen for quite some time, as I'm currently in a major financial crisis at the moment.

Nonetheless, for those who are interested in seeing new devices made available for the 65xx(x) series of processors, give it a read, and let me know what you think about it. Thanks.

Looks good. Not sure if it's the thing would do anything other than make a few bucks after paying for the cost of producing it on a FPGA/CPLD, but would be useful to have around for some of us who aren't going for the asynch bus.

Well, this is the thing: nobody here has told me what, exactly, they want. The most information I've been given was that they wanted a "real bus" so that they could use chips like the 16550 UART and the like. Well, there really isn't anything preventing them from using a 16550 directly with the 6502/65816, so I'm confused as to their rationale for such a thing. I decided to produce the FTS1001 in an attempt to better refine what you hobbiests want: an easier to use, more modern UART (or any similar support peripheral), or something more nebulous, like a bus bridge?

Do you (editorial) want the ISA bus, which adds some semiconductor overhead to any design, or did they simply want a more modern, up to date UART or other peripherals? And, even if your microprocessor runs at 1MHz, you do realize that, technically, the ISA bus runs at 8MHz, right? It's always much easier to design if the CPU is at or faster than its host bus. When the reverse is true, the complexity of the design goes up. DMA support on the part of the peripherals is also greatly complicated, as most peripherals are not designed to handle wait-states. I suppose, though, that this is what you expect to be placed in the chip. Which is fine. But my point is this:

It's very difficult for me to figure out what people want if they don't talk to me!!

The logic to implement the asynchronous bus itself isn't very hard. I can whip that into a Verilog model pretty quickly, and will fit nicely in a a simple PAL chip. In fact, it would be an externalized form of the Wishbone bus, which the 65816 and 6502 processors support virtually automatically.

I've decided to mothball the FTS1001 (as a discrete product) until further interest in it warrents its completion. In the mean time, I'm going to work on the FTS-1002, which implements a native 65816-to-KBus bus interface (KBus is the name I've given the bus for the Kestrel series of kit computers). Here is an incomplete list of features for those who are interested:

* Mode select pin for 6502 or 65816 local bus.
* Fully decodes the 65816's 24-bit address bus.
* 8-bit data bus.
* KBus is a proper subset of the Wishbone bus specification.
* Includes partial address decoding for ROM and I/O spaces.
* Supports bus mastering with external bus arbiter and buffering logic.
* Supports up to 8 external, maskable interrupt sources.
* Supports up to 16MHz operation.
* Up to 16MBps bus throughput.

Hopefully this will gather a little bit more interest.