CTR0 equ $200
CTR1 equ CTR0+1
CTR2 equ CTR0+2
  org $237
start:
;
; blink using a 3-byte counter in memory
;
bl:
  lda   #0
  sta   CTR0
  sta   CTR1
  lda   #40
  sta   CTR2
bl1:
  dec   CTR0
  bne   bl1
  dec   CTR1
  bne   bl1
  dec   CTR2
  bne   bl1
  lda   $C000
  jmp   bl

  org $7FC
  dw start

/******************************************************************************
 UART  - wrapper around the Xilinx Picoblaze uart.
 
 Files required:
   bbfifo_16x8.v
   kcuart_rx.v
   kcuart_tx.v
   uart_rx.v
   uart-tx.v

To connect to arlet's 6502 core, I decode an 8-byte memory location (with SEL).
Base address is the status register when read.  Base+1 is the data register,
which can be read or written.  In the future I may add other registers.
     
******************************************************************************/
module mUART(
  input CLK
, input [2:0] addr
, input SEL
, input WE
, input [7:0] DI
, output reg [7:0] DO
// interface to hardware
, output TX
, input RX
);
//-----------------------------------------------------------------------------
// The UART requires pulses at the rate of BAUD * 16.  At 30MHz, use a 16-bit
// shift register with a single bit on...This provides 115200 * 16 (close to)
wire baud_x16;
SRL16 #(.INIT(1)) baudshifter1 (baud_x16,1,1,1,1,CLK,baud_x16);
//
wire tx_full;
wire tx_half_full;
wire rx_full;
wire rx_half_full;
wire rx_data_present;
wire [7:0] rx_data;
wire do_tx;
wire do_rx;
//-----------------------------------------------------------------------------
// uart tx
//-----------------------------------------------------------------------------
uart_tx utx(
    DI,                     //data to send out
    do_tx,
    0,                      //reset buffer
    baud_x16,               // baud rate x 16 pulses
    TX,                     // output pin
    tx_full,
    tx_half_full,
    CLK);
//-----------------------------------------------------------------------------
// uart rx
//-----------------------------------------------------------------------------
uart_rx urx(
    RX,                 //input pin
    rx_data[7:0],       //input data
    do_rx,              //when strobed, consider read done
    0,                  //rx reset buffer
    baud_x16,           //baud
    rx_data_present,
    rx_full,
    rx_half_full,
    CLK); 
//-----------------------------------------------------------------------------
// mux for the output value: even=status odd=data
always @ (posedge CLK)
  if(SEL & ~WE)
    if(addr[0])
        DO <= rx_data[7:0];
    else
      DO <= {rx_data_present, rx_full, rx_half_full,2'b00, tx_full, tx_half_full};
  else
    DO <= 8'h00;
 
assign do_tx = WE & SEL;
assign do_rx = ~WE & SEL & addr[0];  //any odd address acks read

endmodule

UART_BASE equ $C008           ;C008-C00F dedicated to the UART
UART_STATUS equ UART_BASE
UART_DATA   equ UART_BASE+1

emit:
  tax                 ;move character to x for now
  lda  UART_STATUS
  and  #$02           ;buffer full?
  bne  emit           ;yes, keep trying
  stx  UART_DATA     
  txa
  rts

key:
  lda   UART_STATUS
  and   #$40          ;rx data present?
  beq   key           ;no, keep trying
  lda   UART_DATA
  rts

Logic Distribution:
  Number of occupied Slices:            371 out of   5,888    6%

/******************************************************************************
 a controller for a 128K async SRAM.
 Makes it work like a BRAM
******************************************************************************/
module mSRAM128K(
  input sclk
, input en              //1 means do enable;
, input we
, input  [16: 0] ab
, input  [ 7: 0] di
, output reg [ 7: 0] do
// interface to the real chip
, output [16: 0] xab
, inout  [ 7: 0] xdb
, output  xcs_
, output  xoe_
, output  xwe_
);
  assign xcs_ = ~en;    //chip select is inverted
  assign xwe_ = ~we;    //we is inverted
  assign xoe_ = 1'b0;     //see SRAM timing diagrams
  assign xab  = ab;     //address bus permanently connected
  //
  // Implement a tri-state circuit for the inout xdb
  // Reading a deselected chip should return 0 if pulldowns are enabled.
  wire [7:0] xin = we ? 8'bZ : xdb ; //on read, let data in   
  assign xdb     = we ? di   : 8'bZ; //on write, let data out 
  //
  // Return read result next cycle
  always @ (posedge sclk)
    if(en & ~we)  //on write, output 0 - for some reason it's FF
      do <= xin;
    else
      do <= 8'h00;
         

endmodule

// Memory address selects
assign IO_SEL = (CPU_AB[15:8]==8'hC0); // C0xx
assign BRAM_SEL = (CPU_AB[15:8]==8'hFF)|(CPU_AB[15:9]==7'h00)|(CPU_AB[15:8]==8'h02);//page 0,1,2 or FF use BRAM...
assign IO_C000_SEL = IO_SEL & (CPU_AB[7:0]==8'h0);
assign UART_SEL =    IO_SEL & (CPU_AB[7:3]==5'h1);
assign SRAM_SEL = ~(IO_SEL | BRAM_SEL);


//DI mux.  Since we are careful about setting unselected values to 0, we can just or all of them in
assign CPU_DI[7:0] = BRAM_DO | SRAM_DO | UART_DO;

           Variables in:
          BRAM       SRAM
60MHz      OK        FAIL
30MHz      OK        2x blink
15MHz      OK        2x blink
1MHz       OK        2x blink

bl1:
  dec   CTR0    ;6;
  bne   bl1     ;3;  branch taken