Enso, if you check the accompanying table, it says that the Address Setup time and the Data Hold time are both zero. So, a write cycle is simply Address+WE+Data all valid at the same time for one cycle.
Now, the big question: what happens when you keep WE low for multiple cycles ? I have never tried this myself. At first I assumed it was not allowed, so I always put a read or an idle cycle in after a write. But I did once find a design where somebody had actually kept WE low, and apparently without problems.
My theory is that it should be possible, as long as all address lines change within a very short interval. I figure that in an async SRAM, a glitch on the address lines will cause the wrong cell to be charged. However, since the SRAM cell is built from a pair of inverters, there's a certain amount of charge you have to move before it will flip, and moving that charge will take some time. That's what the datasheet refers to as the write cycle time, which is spec'ed at 10 ns. Of course, the 10 ns is a conservative number, and 5 ns may be enough time to flip the inverter. However, it is unlikely that less than 1 ns would be sufficient. And if you only move 10% of the charge, and then stop, the inverters will quickly restore the previous charge, so there's no residual effect that can build up over time.
So, I think it would be safe to keep WE low for multiple cycles, as long as you make sure there's not too much difference in address line traces.
Edit:
Here's an old SRAM controller I once used on my core. It still has an extra idle cycle after each write to deassert WE.