Hello again,

at this time I have a more complex question. I found the small project here: http://www.6502.org/mini-projects/priority-interrupt-encoder/priority-interrupt-encoder.html
It provides a answer to my question how to distinguish between several IRQ sources. I even understand the trick to use D1 to D3 (instead of D0 to D2) as input for the 74HC574 to create a doubled index for the IRQ jump-table.
Now to the question marks flying around my head ....

As far as I understand the schema, the outputs of the 74HC574 are driving the data-bus (D0 to D7). In the later assembler code the IRQ source is read by


But where is IRQPORT defined? I assume, that it is an IO Address where the circuit is mapped to the memory layout. So do I need some kind of address decoding that matches the specific address and is combined with the R/W signal from the CPU that drives the "READPORT" line? Or do I miss something?

Mario.

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How should I know what I think, until I hear what I've said.

It's been a while since I wrote that article, I had to read it to refresh my memory.

The Read Port line should go low when the CPU reads the address the 74HC574 is mapped to. This address is given the symbol IRQPORT in the assembler as you assumed.

As you deduced, the ReadPort line should go low when the CPU is reading from the 74HC574, so it needs to be created from an address decoder to indicate the correct address and be combined with the Read/Write' signal from the CPU so it only goes low when the CPU is reading from that address and not when it is writing to that address.

If you wish to use the more advanced version, with the interrupt level disable, the WritePort line can use the same address decoding logic, so it is at the same address as the input port, but should go low when the CPU is writing instead of reading. This will put the interrupt priority enable port at the same address as the input port showing what level interrupt has been accepted.

Good luck with your project.

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Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Only if you want to run the CPU at high speed. At 5MHz and below, 74HC logic will be plenty fast enough. It should be good to 10MHz if you don't cascade too many devices in the address decoding.

74AC logic should only be used if the higher speed is really needed. The higher speed of 74AC logic means that it draws more current from the power supply in order to charge the load capacitance faster. This places additional demands on the power supply, circuit board power distribution layout and decoupling and can cause strange malfunctions due to ground bounce and other effects. On a plug-in prototype board, it is not hard to build a system that works fine when built with 74HC logic but misbehaves when built with 74AC logic. Such faults are a nightmare to trace because they happen intermittently and you need very good test gear to detect the glitches. I would recomend that people don't use high-speed logic such as 74AC unless they really need the speed.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

It should be about the same for a given frequency; because although it can charge capacitance faster, that higher current will run for a smaller percentage of eacy cycle's time. So for example twice the current for half the time still comes out to the same amount of charge taken per cycle period, and the same power supply current per MHz. From the "family characteristics" section of my National Semiconductor AC/ACT data book, a 74AC gate typically takes 350µA per MHz with 50pF load. My CMOS books says 74C typically takes about 1.25mw/MHz with a 50pF load which works out to 250µA per MHz, meaning there's not much current difference even though there's more than a 10:1 speed ratio. Obviously board layout is more stringent with 74AC than with one of the slower logic families though.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Thank you for the clarification, I didn't make myself clear! It's the short, high current demands of 74AC (and other fast logic) when it changes state that can cause the problems, as you said.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!