The clouds in my head slowly form into a masterplan for my first board and try to figure out how to deal with the several parts easily.
The first approach will have a 65c02, 8k SRAM 0x0000 to 0x1ffff, 8k EEPROM (0xe000 to 0xffff) and one of the mc6850 that I got cheap on E*ay.
My idea was now, to drive the 65c02 and the 6850 with one oscillator, using a MM74C193N binary counter to divide a 2.4576 MHz clock into a 1.2288 MHz clock for the CPU and a 614.4 kHz clock for the 6850. The clock for the 6850 can internally divided by 64 to a baud rate of 9600.
I already tested this on a breadboard with a 1MHz oscillator (http://www.ichbinzustaendig.de/2013/05/ ... mouse.html) and it seems to work like my scope tells me .
Are there any pitfalls I have to watch for? Is this a good idea to save one component on the board?
Good thing is, that I always get a 50/50 ratio of the clock, even if the oscillator has a different ratio.

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How should I know what I think, until I hear what I've said.

Do make sure you use the '193 (binary), not the '192 (decimal). Also make sure you use 74HC, not 74C. There's a 8:1 difference in speed. If the '193 turns out to be a little hard to get for any reason, the more common way to divide a clock frequency by two is the 74xx74 which has two sections so you can still do it with one IC. The diagram is in approximately the middle of the page at http://wilsonminesco.com/6502primer/ClkGen.html .

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

It is exactly the MM74C193N that I'm using, but it worked well with the 1 MHz clock input. Will I run into problems with 2.45 MHz input? I found it in a pile of ICs that I bought very cheap at http://www.pollin.de. For my first shot I try to use mostly parts that I already have in my little hardware-box. That will make it sometimes harder to get things done, but it is for learning. Following the "second system" approach, the next board will be a feature monster, causing more headaches then the first one

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How should I know what I think, until I hear what I've said.

Assuming it's socketted, you can always put the 74HC part in later if you need to. Even if the 74C part's maximum clock rate is high enough, the output slew rate could be slow enough to cause problems with some circuits. The phase-2 (or phase-0) input of the 65c02 will have enough gain (and may be Schmitt-trigger anyway) that there won't be any problem there, but I have not looked up the 6850's requirements. Do you have in mind doing anything else with the 193's output?

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I think I have a schmitt-triggered NAND also in my box, so I could use it as inverter to get a better square-wave. The clock signals of CPU and ACIA do not have to be in sync, so this should not be a problem.


Not at the moment, the chip count should be as low as possible. I will start with the reset and clock circuit, that can be tested with my scope. After that I will try to get the CPU in a free running mode with $EA on the data lines. I've got some V40511 D to build a small BUS-sniffer that can display HEX values of the address- and data-bus. Because my EEPROM programmer is already working the next thing is to add an EEPROM to the board with some address decoding done by 74hc139 ICs, hoping that I can get a infinite loop running after a reset from the ROM. After that, SRAM is the next on my list.
If this all is successful, things will get more complicated in cause of the hen and egg problem of getting the serial connection running with software (that need working hardware) on the board and hardware (that needs working software to test). I assume that a lot of things that I have to learn are coming

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How should I know what I think, until I hear what I've said.

For lowest parts count, see my diagram here, or my address-decoding page. Near the bottom of the address-decoding page is a picture of a computer made to nearly the same diagram as the first one referenced above, so you can see there's not much there, yet the simpler address-decoding scheme allows a lot more memory and I/O than you're planning for. There is however a serial EEPROM (which we used for storing custom defaults) which you could replace with a half-can oscillator. Two half-can oscillators would take hardly any more room than your '193, so you could make your board smaller. (I used an RC hung on the processor for the oscillator, but you'll need a crystal reference for RS-232, or at least a ceramic resonator.) Actually there's a lot in that 6502 primer that will be of interest to you!

I haven't used the 6850, but I've used the 65c51 different times and it always worked on first try (except when I failed to put a 22pF capacitor on the XTAL input pin).

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I walked through your primer some weeks ago and found a lot of information for my own SCB, also this forum and the whole 6502.org site is a great source of information. Maybe I start with a 6522 VIA instead of a 6850 on the first board. With 2 GPIO ports and the handshake lines I can easily build some "communication" port to my well known AVR minions that provides me a USB-serial connection . So I can concentrate on the SCB basics and add the ACIA later to the board when I can debug properly over the VIA com.

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How should I know what I think, until I hear what I've said.