To be clear, we're just talking about 4KB of data that could be stored in an (E)EPROM. That may be trivial, or not, depending whether your existing ROM has extra capacity available. Another option, FWIW: if the system has mass storage -- SD, perhaps -- then on bootup the character generator data could be copied straight from there to the 8563 or 8568, bypassing the SBC's memory entirely. But, like you, I don't find the 8563 or 8568 to be my cup of tea.

Here's where our preferences differ. I'd rather have the bit-mapped display than the hardware-generated cursor.

-- Jeff

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

The pixel timing is definitely off in places giving thick and thin opposing sides to some of the characters but its definitely usable as an interface for a SBC.

They've tried to cover the chip numbers on the board with a marker pen but it some kind of PIC24F thats generating a feed of colour, font glyph data and attribute bits into the CPLD which then generates the RGB pixel signals. I suspect it uses SPI to clock in the data and that sometimes there is a bit of jitter causing the clock pulses to be uneven.

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Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

A bit, yes -- absolutely! But the problem is far from insoluble. During "stage 1" debugging, the character generator data could reside in EPROM. Then for stage 2 (after mass storage is debugged) that 4K of EPROM space becomes available for application code/data. Other solutions also exist.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Hello,
i'm using MOS8563 in a computer based on 65C816. I tryed to rising dot clock to 25.175MHz to see if VDC can be used to drive a VGA monitor, but the result is negative. At maximum VDC can work stable at 20MHz, but with this dot clock is not possible to obtain the HSYNC = 32Khz in a 80x25 Matrix.
With dot clock = 16MHz can be drived an usual PAL/NTSC monitor (i drive a PAL TV by SCART), and with a dot clock = 20MHz i can drive one very old VGA monitor that can lock HSYNC = 24KHz and VDC work fine (i have some very old VGA monitor, but i found only ONE capable to work at HSYNC = 24KHz).
I have saved from a PC the character ROM and loaded into the memory of the VDC (VGA font 8x16 and VGA font 8x8) and the result was very good.
I have tested the VDC with a uP clock = 4MHz.
For software i starting with the one found in C128 (i found in internet a disassembled version).
Some days ago i have made a new board that use the R6545EAP (the standard R6545A, but capable to work with a character clock = 3.5MHz), and derived the timing from the standard VGA (text mode) dot clock (25.175MHz) and this board can drive a VGA monitor (also a new LCD monitor).
If anyone have interest in this, can tell me the schematics for the VDC solution and/or for the R6545EAP solution (also work with an HD6445).
In this last board the video RAM is shared with uP (as opposite with the VDC), but the access from uP is synced (by RDY line) so that the CRTC and uP have unimpeded access to video RAM.

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http://65xx.unet.bz/ - Hardware & Software 65XX family