Arlet wrote:
Windfall wrote:
Okay, I see. You've shifted the paths a little by preprocessing the opcode while it's not even registered yet.
In my core, the opcode is never registered. None of the incoming data bus is registered before processing.
Well, you do register it. Just in processed form. Which requires faster memory. But I suppose there are always tradeoffs to consider.
Arlet wrote:
Quote:
See what happened here ? The critical path may have become shorter here, since this replaces the memory access path with a combinatorial path involving only PW and the two least significant bits of the PC.
It only becomes shorter if PW/PWA are registers. But then you'll have to add the cycles to load those registers. In addition, you'll need muxes to grab the operand values.
I already said they were registers. And they're loaded at the same time as IR (their values are not needed until the next instruction), so there's no penalty.
Arlet wrote:
And what are you going to do when you load data ? If you use the same method, every LDA will require an extra cycle.
And did you consider STA ?
I explained all that before. Data could go via 'NOT request_instruction' and could arrive at the core as anything it chooses to be. Including directly.
Please do me and others the courtesy of reading what has been said and letting it sink in for a while before you react. I have to repeat myself endlessly, and I'm sure I'm not the only one annoyed by it.