You can eliminate many wires by placing control line name on top of transistor gate input.
By the way, there are two internal address buses : ADL (address low) and ADH (address high).

_________________
6502 addict

I think the difficulty here is the conflict between wanting to show everything and showing how things are connected. I think the diagram has become cluttered because it's too small and it shows too much. Some ideas:
- remove as many jogs as you can, by making space.
- remove the hoops for no-connect crossings. The modern convention is to place a blob at a connection point (and always use T-junctions - never connect at a crossing)
- tone down the power and ground lines. They are the least interesting wires, but they are highlighted in colour
- don't try to route all global connections: use labels and symbols. Power and ground should appear as local connections to symbols.

Cheers
Ed

Hi Ed,


Ok, I will try to make schematic looks better. Thanks for your suggestion.


Are you referring jog like solid circle between two wires? If three or four wires are connected together, no jog and use T-junction?


Are you referring hoop like half circle line across the wire? T-junction may not be helpful because crossing is needed. The bridge may be the answer. What is another option?

Take care,
Bryan Parkoff

Hi Bryan
Not quite... let me try to clarify...


No, I'm using "blob" to mean a solid circle. By "jog" I mean all the short segments, dog-legs and close following which your wires do: better that you have fewest corners, because it's easier for the eye to follow.


Yes, by "hoop" I mean the half circle where a wire jumps over another. What you mean there is that two crossing wires do not connect. I suggest that the two wires should simply cross. The absence of a blob means that they don't connect. As an extra suggestion, to make it even less ambiguous, you also make sure that wires which do connect - where you will use a blob - never connect at a crossroads. You arrange instead that every connection - every blob - is at a T-junction. So there are only two allowed forms: a cross with no blob, and a T-junction with a blob. No hoops, and so again it is easier for the eye to follow.

Hope this helps
Ed

Hi Ed,



In my opinion, an absent blob on two wires is not helpful. Maybe, I should add two colors. The vertical wire is dark gray and horizontal wire is light gray. If blob is not absent, it will be normal gray rather than dark gray and light gray. They look more clear. What do you think?

Take care,
Bryan Parkoff

Give the pure approach a try. You'll soon get used to it. I must have come across these two styles in the mid-70s, and the hoops style was described as outdated at that time.

The hoop jumps were going out when I, too, was getting into electronics in the 70's. As miniaturization and falling prices of active devices made it practical to achieve much more complex circuits, draftsmen were spending way too much time drawing all the little jumps. A simple cross (with no hoop) also made the diagram easier to look at.

Getting rid of as many jogs as possible definitely helps readability. The preference (not a requirement) of making connections to be only T and not + was based on limitations with copy methods, and the possibility of a dot either forming or disappearing at the middle of the +. We don't need to worry about these anymore with laser printers that do 600 dpi or more, and the blueprint process is no longer needed as we can get high-quality photocopies of E-size and larger papers. Nor do we ever have to make 12th-generation photocopies anymore. I think the situation now avoids problems with using a connecting dot on a +, and doing so reduces the number of jogs in a diagram, making it more legible. I have come to prefer this, although I still make the dot as big as practical without making it exaggerated.

There are times when a common ground point (not bus) is needed, and must be shown. In that case there might be several lines going into a single dot, which also means the lines will come in at various angles. This is usually for preventing unwanted noise coupling though, as in A/D and D/A circuits, so I wouldn't expect to see it in a circuit for a microprocessor.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi,

I ask a question. The transistor is t2083 near bit 0 of data bus. What is this? It sounds like pull-down transistor to the ground. The drain is connected to db0 (1005), gate is connected directly to the drain, and the source is connected to the ground. When the power is turned on, how can the pull-down transistor work?

Take care,
Bryan Parkoff

That's a protection diode! You may have to consider elevated voltages to see how it functions. All the inputs have them, I think.
Cheers
Ed

Looks like diode protection.

_________________
6502 addict

BigEd, you win

_________________
6502 addict

That was close!

Hi,

I reviewed Ed's advice about redrawing schematic. I revised the schematic. It is now looking better than before. I drew differently according to my decisive design.

The blue box is changed to grey. Sub-sub-sub box is dark grey. Sub-sub box is normal grey. Sub box is light gray. Main box is white. From dark gray to white is easier to hide full complex details. All the wires can have any colors, but they exclude red, green, grey, and white.

The '-' sign or minus sign is a blob connected to two wires. The blob is white so that you know left wire is blue and right wire is purple. More colors are helpful than single color if you follow the white blob.

The '+' sign or plus sign and 'T' junction are blobs in any dark colors. Three or four wires are connected together into blob.

The hoop is replaced to the broken line and solid line.

The schematic is very small in reduced size. You can use zoom to enlarge it. Small size is preferable when you want to add it to the large schematic.

The label of transistor number and node number are included in each transistor. The node number is only the number without name such as 943 and it does not have name clock 2. It can help you to identify the node number when you locate the transistor number in the transistor table. The node number is in the gate position. If you want to know the node number in source or drain, then look at another transistor's gate and find the node number.

Not all node numbers will be shown unless two transistors are ANDs.

The node names are on the wire between two transistors. They are readable so that you don't have to pay attention the node numbers.

I put transistor table into Microsoft Access. I use it to draw my schematic instead of looking at the visual 6502 website. Sometimes, I am unable to locate the transistor numbers in the visual 6502 because the mouse pointer attempts to click the transistor, but other wires across transistor is blocked such as violet transistor as protection ground and some hidden "pull-down" transistors.

Here are two pictures. One is low program counter register and another one is high program counter register. Let me know what you think!

I will finish all the registers before I can continue Random Control Logic and instruction set table.

Last time, we discussed about decimal code's half carry. I wanted to know why half carry is not set when low nibble becomes zero and high nibble becomes one. I am going to solve it and find answers soon as I begin to draw ALU schematic and I will study it. I will have better explanation what is going on at later time.

Low Program Counter Register:


High Program Counter Register:


Take care,
Bryan Parkoff

Hi, Ed, I still ponder your comment about D latch. A D latch with two nand gates is safer because it has "closed box" which invalid inputs are blocked or provide value zero as reset. Two inverters and two pass gates have "opened box" while allowing to manipulate invalid inputs. Random Control Logic and opcode tables can take care of it.

What happen if A register has value one while SBAC and phi2 are high and value one is coming from SB? No data is affected as long as value one remains unchanged. In other words, what happen if A register has value zero while SBAC and phi2 are high and value zero is coming from SB? No data is affected as long as value zero remains unchanged like reset.

If SB has value 1 and A register has value zero, then data in the A register will be corrupted while SBAC and phi2 are high.

A0 (737) and node 146 hold value one while node 5 holds value zero. What happen if phi2 is low while node 737 and node 146 are disconnected? How long can node 737 hold value one before phi2 raises high again? If wait is too long, node 737 will degrade until value one becomes value zero and value in the node 5 will change one from zero.

Bryan Parkoff

It may be that a pair of NAND or NOR gates is a safer implementation of a D-latch, but there are very few D-latches like that on 6502. Is the aim to model what we have or to model what we'd prefer to have?

We are agreed that it is undesirable to have both SBAC high and Phi2 high is a problem. The question is how to model it, or whether to model it. The 6502 doesn't do that (I think) because the control lines are conditioned elsewhere, upstream of the drivers. If the circumstance doesn't arise, there's no need to model it, unless you specifically want a general and encapsulated model of the D-latch as implemented. In which case, I suggest you model as '0 wins'

You are quite right that the very widespread idiom of using dynamic charge storage as the basis for latches and flip-flops has a problem with charge leakage. That happens on a timescale of milliseconds, whereas normal operation is on a timescale of nanoseconds to microseconds. So again in practice there's no need to model this. If you really wanted to model it you could, at the cost of complexity and with a verification problem.

The point of a model is to leave out the unnecessary details!

Cheers
Ed