Hi,

I put together a tutorial for making sense of the mess of colored lines that is Visual 6502 (and other sims based on the same framework) for the nesdev community at http://wiki.nesdev.com/w/index.php/Visu ... t_tutorial . It focuses on Visual 2A03 (the NES CPU, which also contains sound circuitry among other things) and Visual 2C02 (the NES PPU), but many sections should be universal.

Thought people here might find it useful too.

Good stuff! Thanks for that.

One point: you speak of gates being open and closed. I think that might be unclear. (It's unfortunate that "gate" could mean logic gate, transistor or the gate terminal of a transistor, in different contexts.) It might be clearer to speak of transistors being on, or channels conducting. If you're speaking in terms of switches - and I usually think of transistors as switches - then "open" means the switch is off and there's no connection, while "closed" means the switch is on and there is a connection.

Hopefully you can find a way to re-word things so it's more clear!

I can link to your page from the visual6502 wiki - especially if you have some idea where that link should go.

Cheers
Ed

Thanks!



I take it "on"/"closed" and "off"/"open" are the right terms to use in the context of gate terminals and switches then (might've taken the door analogy a bit far in my head ). Looks like I could just do a simple substitution, and maybe get the word "switch" in there too since it'd be nice to cover.



I'm not familiar with the layout of the wiki, but some introductory or user's guide part might make sense I guess.

"Power sources" are depletion-mode transistors, which is slighty differ from usual enchancement-mode transistors with additional insulation under its gate.

http://citstudents.in/download/Notes/EC ... -NOTES.pdf

nMOS NAND gate:


PPU OAM and palette memory are both technically SRAM, as its formed by pair-couple of inverters.

DRAM is made of isolated gate latches.


Both planes are multiple NOR-gates.

Not for me I imagine transistor as water tap. When tap is open - water (electricity) is flowing

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6502 addict

Updated the page to switch the "open"/"closed" terminology. Proofreading would be welcome.

Edit: Reverted for now; see below.

Are you sure about that? The cells in the OAM are not directly connected to power, rely on capacitance, and require refreshing not to fade (which the article covers).



The right-most plane can be viewed as an AND plane built with NOR gates though. If it's wrong, than what would an "actual" AND plane look like?

Re. "open" and "closed" for the transistor gates, I'd like to go for the most "standard" usage if there is one. Is this a matter of preference with a relatively even split, or is one much more common?

Edit: I reverted the switch for now just to not confuse the heck out of people working through the article. Might switch back later after some more confirmation.

As far as I seen, all PLA's are made of multiple NOR gates. The difference is only in horizontal/vertical layout.

In case of your example :

I can see two PLA's: one with horizontal outputs which feeds another one, with vertical outputs.


DRAM require additional refresh controller.

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6502 addict

I'm going by the terminology in e.g. http://en.wikipedia.org/wiki/Programmable_Logic_Array . I think viewing the "AND" part as just that makes the most intuitive sense in this case too.

As the article mentions, there is no automatic refresh logic for the OAM in the PPU. It (usually) gets away without it since sprite evaluation will read the entire OAM for each scanline. (It can cause glitches if rendering is turned off and values are allowed to fade for too long though.)

Re. enhancement and depletion mode, that would be nice to cover at a basic level.

Does the depletion-mode transistor act as a "resistor" by lowering the conductivity of the channel as more current gets through through the "hook", until an equilibrium is reached?

It seems to be a hybrid between SRAM (pair of inverters) and DRAM (no power supply to cells)

This made to prevent erasing of OAM and palette RAM.

_________________
6502 addict

How about using "on" and "off" instead of open and closed?

As for pull-ups: it's possible to design using ordinary (enhancement-mode) transistors - the 6800 did this - but more efficient to use depletion mode. It's a transistor like any other, but with a lower threshold voltage and therefore more on-ness than an ordinary one. In fact, it's never off. It's just about on when the input is low, and strongly on when the input is high. From a distance, it certainly is very like a resistor (and a resistor would also work) - the details of the waveform will be different, as the output goes high or low according to the pulldowns.

Cheers
Ed

Sounds reasonable. I thought "the gate is on" sounded weird at first, but maybe not.

Transistor (as switch) can be "on" or "off". Gate (as door) can be "open" or "closed".

BigEd, nice explanation!

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6502 addict