Hi,
BigEd wrote:
I look forward to news on your simulator project! (Eventually!)
Hi Ed, I plan to create two different 6502 simulator projects. They are written in C++.
First one is bit by bit called slow simulator such as transistor by transistor like true Visual 6502 Simulator. The Visual 6502 Simulator is considered to be incomplete because most nodes do not have good node name. Look at the Visual 6502 circuit and it is difficult to understand while you are trying to trace the behavior of some transistors. You will spend few or many hours to figure out how transistor by transistor works.
Second one is byte by byte called fast simulator. Group some transistors into one function like the number of reduced transistors and omitted extra transistors. When function is called, any byte value in register or memory will be performed fast than individual bit.
I can ask Visual 6502 designer's permission when I can add good node names in the nodenames.js if he is interested.
He did mention that 99% simulator is perfect, but it has eight errors. What are eight errors? He claimed to say 100% accurate. Did he fix eight errors already?
Did he fix 'rdy' pad or make it be simulated correctly? Did he fix half carry output from ALU in decimal adjustment? I did see his notes. I will like to know if everything has been fixed already.
I can show you transistor images.
Attachment:
A0_a.png [ 16.73 KiB | Viewed 863 times ]
The transistor image has PMOS transistor and NMOS transistor. I added power on top of PMOS transistor and ground on bottom of NMOS transistor.
Look at second image below.
Attachment:
A0_b.png [ 16.42 KiB | Viewed 863 times ]
It has NMOS transistor and pull-up transistor. Is second image the same as first image?
Look at third image below.
Attachment:
A0_c.png [ 17.65 KiB | Viewed 863 times ]
It has two NMOS transistors. They both have pull-down and pull-up. The inverter must be added to pull-up transistor in order to prevent short circuit.
Is third image the same as first image?
org wrote:
Quote:
I am going to study transistor by transistor while drawing schematic.
This job is already done.
viewtopic.php?f=8&t=2208http://breaknes.com/files/6502/6502.jpgThanks for showing the schematic picture. Unfortunately, I am not satisfied. The schematic picture does not provide full detail information about all transistors. I already showed you three images.
They are painted in color. The color can help us to understand what each transistor is doing.
The red transistor has two states: one bit OR Z (disconnected).
The green transistor has two states: zero bit OR Z (disconnected).
Both red transistor and green transistor can only have one direction (not tri-state).
I will show you another transistor in the bottom of my post.
The gray transistor has three states: one bit OR zero bit OR Z (disconnected). It can have one direction OR bidirectional like tri-code. It is considered to be switch.
When we see the color, we do not need to see two labels: Vcc or Vss.
Now, I am showing you my own schematic picture. I drew Clock Generator schematic. It has all transistors. I grouped some of them together into NOT and NAND. I will add NOR, AND, and OR later. I have to be careful when some transistors are series-parallel and they are considered to be NAND and some of them are series and they are considered to be NOR.
Some groups of NOT and NAND are easier to be understood as long as they DO NOT represent to be real NAND, but just only inverter.
Attachment:
Clock Generator.png [ 52.6 KiB | Viewed 863 times ]
Finally, here is another schematic picture. I drew Accumulator Register schematic. As I mentioned earlier, it shows gray transistor.
Attachment:
Accumulator Register.png [ 91.35 KiB | Viewed 863 times ]
You may notice that some of my labels are different from Visual 6502's labels. Look at this table below. You will see 'Old Label' is Visual 6502's labels.
Code:
Node New Label Old Label Description
1171 clk0in clk0 External Clock 0 Input
358 not_clk0 none Inverted Internal Clock 0
1715 clk0 none Internal Clock 0
1399 enable_clk1 none Enable Internal Clock 1
1129 enable_clk2 none Enable Internal Clock 2
1105 none none Output Power or Ground of Clock 1
1467 none none Output Power or Ground of Clock 2
710 clk1 cp1 Internal Clock 1
943 clk2 cclk Internal Clock 2
657 power none Enable Power
558 ground none Enable Ground
519 not_clk0 none Inverted Internal Clock 0
670 clk0 none Internal Clock 0
747 enable_clk1out none Enable External Clock 1
127 enable_clk2out none Enable External Clock 2
1417 none none Output Power or Ground of Clock 1
135 none none Output Power or Ground of Clock 2
1163 clk1out clk1out External Clock 1 Output
421 clk2out clk2out External Clock 2 Output
Please give me feedback what you think about my two schematic pictures. Are they easily understood with full detail information?
Take care,
Bryan Parkoff