Looking through Garth's 6502 primer I found the hint, that several 6551 can be driven by one crystal by using the XTAL output of the first ACIA to drive the XTAL input of the next one.
So my idea was to drive also the Phi-0 input of the 6502 by that clock signal.

There could be different ways to clock the board:

For CMOS Chips:
Can I use a 5V 1.8432 MHz oscillator to drive the XTAL input of a 65C51 and and the Phi-0 of the 65C02? Or use a 3,6864 MHz oscillator with a Flip-Flop to generate a clean 1.8432 MHz square-wave with an accurate 50% duty-cycle?

For NMOS Chips:
Use the 1.8432 MHz crystal as clock-source for the 6551 and then use the XTAL2 (out) also as source for the 6502?

Sorry for that maybe stupid question, but my knowledge for this part of electronic is very poor.

Mario.

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OK, I already thought that this is not a "best practice" approach. It was more a "esoteric" question. Even if there are no good reason to do this, would it be possible only from a technical point of view?
So the Commodore 64 was running with 985248 Hz (PAL version) using a master clock with 17.734475 MHz (devided by 18 for the cpu clock), so they should had the same problem with proper timers. The frequency is closer to a plan 1MHz, but still there should be an incrementing difference.

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If you are not bothered about running your CPU at 1.8432 MHz, this is certainly technically feasable and I see no reason why it should not work.

Years ago I modified an Acorn Atom to have a 1.78977 MHz clock for the CPU and apart from having a non-standard tape interface speed the system ran with no ill effects. Running the CPU at this speed allowed me to synchronise the CPU with the 6847 display chip and eliminate on-screen noise when the CPU accessed the video memory.

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The oscillator output should drive both inputs but separate oscillators with sockets would be best. It would also be a good idea like you mentioned to use the flip-flop for the 65C02.

Where you have the two versions you label, "For CMOS Chips:" and "For NMOS Chips:", I can't think of any reason not to run both types the way you give under "For CMOS Chips:". For minimal systems, you could do that, but as others have said, setting up timers in the VIA might be easier to get the values you want if you run the processor at an even value like 2MHz or 4MHz. And actually, all the current-production parts can go much, much faster if the board construction is up to it, so having the duty cycle way off won't hurt anything at the speeds you're talking about. (This page of Jeff's shows the idea very well with repeating motion pictures of timing diagrams.) So if you wanted to just hang a crystal on the '51 and run the its crystal output to the phase-0 input of the processor, I don't anticipate any problem there either. Bare crystals are hardly any cheaper than complete crystal oscillators, so this would mainly be to save board space, not money.

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

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Yes or no, depending on the assumptions. There are specifications for clock pulse width low, clock pulse width high, and for the overall cycle time. If you need to operate the chip at its maximum frequency (shortest possible cycle time), the numbers usually are such that the low and high times will be equal, incidentally yielding 50% duty cycle. But AFAIK none of the 65xx processors -- NMOS or CMOS -- directly specifies what the duty cycle must be. IOW, if maximum operating frequency is not required then you have leeway to deviate from 50% -- perhaps very drastically. Garth touched on this point earlier, athough without elaboration: cheers,
Jeff

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I don't think this will cause a problem. The baud-rate clock can be driven from a seperate oscilator to phase-2 and not cause any problems, even when the two oscilators are not synchronised. With unsynchronised clocks, worst-case timing clashes are bound to occur sooner or later, and since the 6551 doesn't suffer from this problem, I think we can assume that there are no timing requirements between the baud-rate clock and the phase-2 clock. As long as the 6551's phase 2 input is connected to the 6502's phase 2 output, it should work.


Very true. The Oric-1 computer used a 2MHz 6502 with a 1MHz clock with a 2-1 duty cycle. The video system performed 2 memory accesses when phase 2 was low, then the CPU had access to memory when phase 2 was high. This required a 2MHz 6502 and a 2MHz 6522 even though the clock frequency was 1MHz because the phase 2 high time - a third of a cycle - wasn't long enough for 1MHz devices, but it didn't cause any problems either with the CPU or the VIA.

_________________
Shift to the left,
Shift to the right,
Mask in, Mask Out,
BYTE! BYTE! BYTE!

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I think it's always a good idea to start a micro processor project with a quality 'clockpulse' . It's one less thing to worry about if you do end up dealing with some other possible timing issues after constructing your project. The flip-flop output provides quality fast rise/fall times and a 'very' stable 50% duty cycle. A crystal (or other types) oscillator duty cycle may vary with temperature and time. Maybe not vary much but it could be at some point the deal breaker on a close timing sequence when accessing ram, rom or i/o when your dealing in ns timing.

The 65c02's phase-0 input is Schmitt-trigger, so what you feed it does not have to be very clean. If you use the RC clock option, the capacitor's charging and discharging keeps that input going through an analog range. We sold a lot of high-end intercoms that went into private aircraft, weather-research aircraft, and some non-combat military aircraft (like large transports) with a 2MHz Rockwell 65c02 controlling them and using the RC oscillator option at close to 1MHz. Duty cycle was something like 60-40. It was never a problem.

How you handle the clock signal (phase-2 out, in the case of the '02) to the rest of the system OTOH is a different story. Also, the 65816 requires a really clean clock signal since it does not pre-process it before sending it out to the rest of the system like the '02 does.

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The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

[...]

GARTHWILSON wrote:

The 65c02's phase-0 input is Schmitt-trigger, so what you feed it does not have to be very clean. If you use the RC clock option, the capacitor's charging and discharging keeps that input going through an analog range. We sold a lot of high-end intercoms that went into private aircraft, weather-research aircraft, and some non-combat military aircraft (like large transports) with a 2MHz Rockwell 65c02 controlling them and using the RC oscillator option at close to 1MHz. Duty cycle was something like 60-40. It was never a problem.

"clockpulse's" comment about a quality clock pulse is good, though. A beginner doesn't want to accidentally introduce too many subtle variables that can sabotage the design before it even gets out of the gate, so to speak. An asymmetric clock is one of those variables that in itself might not cause trouble. When combined with marginal timing however...

Quote:

How you handle the clock signal (phase-2 out, in the case of the '02) to the rest of the system OTOH is a different story.

Note that the WDC 65C02 data sheet has something to say about that:

3.8 Phase 2 In (PHI2), Phase 2 Out (PHI2O) and Phase 1 Out (PHI1O)
Phase 2 In (PHI2) is the system clock input to the microprocessor internal clock. During the low power Standby Mode, PHI2 can be held in either high or low state to preserve the contents of internal registers since the microprocessor is a fully static design. The Phase 2 Out (PHI2O) signal is generated from PHI2. Phase 1 Out (PHI1O) is the inverted PHI2 signal. An external oscillator is recommended for driving PHI2 and used for the main system clock. All production test timing is based on PHI2. PHI2O and PHI1O were used in older systems for system timing and internal oscillators when an external crystal was used.

Emphasis added. Bottom line, as I said, is you won't get extra brownie points for using an idiosyncratic clock source. I would not use either of the 'C02's clock outputs in a new design, but that's just me being conservative.

Quote:

Also, the 65816 requires a really clean clock signal since it does not pre-process it before sending it out to the rest of the system like the '02 does.

This is a case where the clock oscillator should be run through a flip-flop and the flop's Q or /Q output used to drive PHI2 on the '816. Note that the '816 does not produce a PHI1O or PHI2O like the 'C02 does. If you need the equivalent of PHI1O and PHI2O in an '816 system, take one off of Q and the other off /Q. You'll have a two-phase, overlapping clock with very sharply defined edges and 50 percent duty cycle.
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EDIT: Fixed an egregious typo that would have confused someone not familiar with flip-flop outputs.

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