Hi Bryan
even with attachments, there's a button which allows you to place them inline. If your image is someone on the web - at a photo-sharing site for example, just paste the *.jpg URL inbetween your img...img tags. Optionally, you can surround the img...img with url...url tags to allow a clickthrough to an URL of your choice.

The node 943 (cclk) includes a pad between clk0 and RnW - this pad is not bonded to a pin on the 6501. On the 6501, which was pin-compatible with the 6800, this pad is bonded to pin 36, DBE - in this case the node is not driven by transistors on-chip, but by the off-chip clock generation circuit. On the 6502, cclk is driven by transistors like t3059, and, tracing back, ultimately by clk0. To trace forwards, start at t2120.

I look forward to news on your simulator project! (Eventually!)

Cheers
Ed

This job is already done.

viewtopic.php?f=8&t=2208

_________________
6502 addict

Hi,


Hi Ed, I plan to create two different 6502 simulator projects. They are written in C++.

First one is bit by bit called slow simulator such as transistor by transistor like true Visual 6502 Simulator. The Visual 6502 Simulator is considered to be incomplete because most nodes do not have good node name. Look at the Visual 6502 circuit and it is difficult to understand while you are trying to trace the behavior of some transistors. You will spend few or many hours to figure out how transistor by transistor works.

Second one is byte by byte called fast simulator. Group some transistors into one function like the number of reduced transistors and omitted extra transistors. When function is called, any byte value in register or memory will be performed fast than individual bit.

I can ask Visual 6502 designer's permission when I can add good node names in the nodenames.js if he is interested.

He did mention that 99% simulator is perfect, but it has eight errors. What are eight errors? He claimed to say 100% accurate. Did he fix eight errors already?

Did he fix 'rdy' pad or make it be simulated correctly? Did he fix half carry output from ALU in decimal adjustment? I did see his notes. I will like to know if everything has been fixed already.

I can show you transistor images.


The transistor image has PMOS transistor and NMOS transistor. I added power on top of PMOS transistor and ground on bottom of NMOS transistor.

Look at second image below.


It has NMOS transistor and pull-up transistor. Is second image the same as first image?

Look at third image below.

It has two NMOS transistors. They both have pull-down and pull-up. The inverter must be added to pull-up transistor in order to prevent short circuit.
Is third image the same as first image?


Thanks for showing the schematic picture. Unfortunately, I am not satisfied. The schematic picture does not provide full detail information about all transistors. I already showed you three images.

They are painted in color. The color can help us to understand what each transistor is doing.

The red transistor has two states: one bit OR Z (disconnected).
The green transistor has two states: zero bit OR Z (disconnected).

Both red transistor and green transistor can only have one direction (not tri-state).

I will show you another transistor in the bottom of my post.

The gray transistor has three states: one bit OR zero bit OR Z (disconnected). It can have one direction OR bidirectional like tri-code. It is considered to be switch.

When we see the color, we do not need to see two labels: Vcc or Vss.

Now, I am showing you my own schematic picture. I drew Clock Generator schematic. It has all transistors. I grouped some of them together into NOT and NAND. I will add NOR, AND, and OR later. I have to be careful when some transistors are series-parallel and they are considered to be NAND and some of them are series and they are considered to be NOR.

Some groups of NOT and NAND are easier to be understood as long as they DO NOT represent to be real NAND, but just only inverter.


Finally, here is another schematic picture. I drew Accumulator Register schematic. As I mentioned earlier, it shows gray transistor.


You may notice that some of my labels are different from Visual 6502's labels. Look at this table below. You will see 'Old Label' is Visual 6502's labels.


Please give me feedback what you think about my two schematic pictures. Are they easily understood with full detail information?

Take care,
Bryan Parkoff

Hi Bryan
a lot of work went into those, I would think!

I think I like the idea of redrawing the schematics with the pass gates represented as tristate buffers. This won't work everywhere but it will work most of the time. I'm not sure about the idea of trying to show everything all in one picture. For example, once someone has understood that an inverter has power connections as well as signal connections, I think it might make things less clear to include the power connections. Maybe it's a good idea for one or two circuits, but to do the whole chip this way is to lose the power of abstraction.

Of course that's only my opinion! By all means proceed as you see fit. The more people tackle this with their different tactics, the more we might learn about how to explain and understand a transistor-level circuit.

I still think it would be much better to represent the input mux of the ALU register with a left-to-right signal flow everywhere. The only right-to-left flow should be the feedback to the input of the clock-controlled pass gate. This way, all your logic gates point in the same direction.

I'm part of the visual6502 team and I can add nodenames. I won't be changing existing names, though, because that might break existing URLs. You are free to make a fork of visual6502 - indeed you can fork it and then have github serve your site, by putting your updates into a branch called gh-pages. In your fork you can of course change names.

Cheers
Ed

Be sure to break the connections between input and output on your first and third diagrams. You have the input internally shorted to the output.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I should add: I believe there are no errors in visual6502. Errors during the layout tracing were all cleared up before the website went live (which was a week or two after I got involved)

Hi Ed, of course, redrawing schematic is too much work to do. I am willing to invest my time!


To look the whole chip is difficult to understand because it is too complex. We try to break the complex into simple schematic. When you look at it, it has hidden all the full detail information. For example, Accumulator Register is white box with input and output and the whole chip is black box.

When you zoom Accumulator Register, you will be able to see full detail information in the white box.


I agreed. Sometimes, input to output is left-to-right signal and sometimes, they are right-to-left signal such as an example of Clock Generator you saw it in my schematic picture.

The gray square acts to be gray box (like blue box) and it describes External Clock Generator and Internal Clock Generator. The white square acts to be white box hides two gray boxes and shows one Clock Generator with one input and four outputs.

Do you like my schematic picture?

Take care,
Bryan Parkoff

Hi Ed,

I want to add. When we talk about transistor, it is wise not to label NOT, NOR, and NAND "between power and output" and "between ground and output". The confusion can be reduced while concentrating SWITCH, OR, and AND. When we talk about between power and output, we say we want to turn on the power as "1" and nothing as "0". When we talk about between ground and output, we say we want to turn on the ground as "1" and nothing as "0".

After we finish concentrating the transistor, we can talk about input and output as we can label NOT, NOR, and NAND. For example, OR is 0, 1, 1, 1 and all 3 "1" represents ground and "0" represents nothing. Now, begin to think to do invert as we can think power as "1" and ground as "0" to be shown as NOR.

I am sure my schematic will look more clear.



I redesigned my schematic so that symbols take too much space, but blue box can reduce the space. Sometimes, people don't like to see red wires and green wires connected to the power and ground. The red wire represents "1" and green wire represents "0". It is easier to concentrate gray wires and gray wires represent both "1" and "0" and "disconnected".

I drew the low program counter register as you recommended from input to output. Please look at it. Offer feedback what you think!

Take care,
Bryan Parkoff

Hi Ed,

I have no idea what four transistors are. Four transistors are t2736, t2221, t1750, and t1101. They are located in Bit 0, Bit 1, Bit 2, and Bit 3 of the High Program Counter Register. They are connected to adl0, adl1, adl2, and adl3. All of them are connected to the power. If they are gated to the ground while transistor is turned on during clock 2, then the power and ground will be caused to become short circuit. It does not make any sense.

Bit 4, Bit 5, Bit 6, and Bit 7 of the High Program Counter Register do not have four extra transistors. Do you have idea? Strange.

Take care,
Bryan Parkoff

Bryan, other 4 transistors are located near lower part of PCL register.

This thing is called "bus precharge". All internal 6502 buses are connected to VCC during PHI2.
The reason is that the discharge of the bus from 1->0 is faster, rather charging from 0->1. So during "read phase" (PHI2) 6502 is precharging all buses, and during "write phase" (PHI1) some bits of bus are discharged to zeroes and other kept as ones.

_________________
6502 addict

Ok, I will remember when I continue to draw more schematic. I posted one schematic with full details. Please tell me what you think when you looked at it.

Take care,
Bryan Parkoff

I think its too complicated and overburned by interconnections. Also you are using alien notation of well known buses and signals

_________________
6502 addict

I am not sure I understand your comment. Please clarify.

Take care,
Bryan Parkoff

You have too many wires.

_________________
6502 addict

Too many wires are very normal. I don't believe they are complicated. When you look at visual 6502, you will see thousands of wires. Thousands of wires are too complicated. The only best method is to group wires and transistors into one white box or blue box. The white box shows one 8 bit input, two 8 bit outputs, and six options. Read the label so that white box is less complicated. When you want to see full detail, look at group blue box and subgroup blue boxes.

Don't pay attention to these wires. Just look at the label of blue box and colorful transistors.

Maybe, eight wires should have color rather than gray, but I don't think it is necessary.

Take care,
Bryan Parkoff