ElEctric_EyE wrote:
So the objective would be to discard the first address output in these cases, since the second address output is the corrected one?
Yes, but since you can't "discard the address", this would involve the extra RD signal. So, for instance, in the indirect Y mode, the state machine goes INDY2->INDY3 or INDY2->FETCH. In the first case, there's a dummy read in INDY2, so you should deassert RD in INDY2 when it's followed by INDY3. Alternatively, you can remove the INDY3 state altogether, and do a 16 bit address calculation instead. The extra cycle comes from the fact that the 8 bit ALU needs two cycles to calculate the address.
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I don't think correcting branch opcodes would be an issue for address decoding though, or would it?
The branches should be fixed in the same way. When BRA1 is followed by BRA2, don't assert RD during BRA1. Or, do a 16 bit address calculation when adding PC to branch offset.
My preference would be to try to add 16 bit address calculation. It's a simpler solution, and performance may not suffer too badly because there will be a dedicated adder in the address path, rather than using the ALU.
Note that on 65org16 you need to do a 32 bit address calculation rather than a 16 bit one.