Concept & Design of 3.3V Parallel 16-bit VGA Boards
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ElEctric_EyE
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Here are the speed comparisons for the Concentric circle fill (239 circles), showing the speed of the original code on top, the use of 4 65O16.b accumulators in the middle, then 6 accumulators plus some help from Arlet in the final optimization of the software. The number of cycles can be seen to the lower left of each pic.
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ElEctric_EyE
- Posts: 3260
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Arlet wrote:
A useful feature in your hardware may be to add a programmable offset in your address calculation. This would allow you to set the origin of the circle at the beginning of the plot routine, and then the rest of the routine can just plot around (0,0) without having to keep track of the offsets.
Code: Select all
always @(posedge clk) begin
if (osetCS && cpuWE && !cpuAB[0])
osetREGL <= cpuDO;
if (osetCS && cpuWE && cpuAB[0])
osetREGH <= cpuDO;
end
always @* begin //optimize the videoRAM address for plotting (X,Y) in the (LSB,MSB) for indirect indexed
cpuABopt [20:19] <= 0; //bank bits
cpuABopt [18:10] <= cpuAB [24:16] + osetREGH; //Y[8:0]
cpuABopt [9:0] <= cpuAB [9:0] + osetREGL; //X[9:0]
end-
ElEctric_EyE
- Posts: 3260
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
After 16 runs, the best timing score it could do was 84.
I don't think offsets would be useful for lines though. I'll work on that next
I don't think offsets would be useful for lines though. I'll work on that next
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ElEctric_EyE
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Daryl, stupid question but what variables get plotted in your Bresenham line? IX and IY?
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
ElEctric_EyE wrote:
Daryl, stupid question but what variables get plotted in your Bresenham line? IX and IY?
As a quick speed enhancement, you could shift both DX and DY left until the msb of either is 1, this will reduce the loop interations. (If this point is not clear, let me know and I will expand my explanation).
If you need any more help, just ask!
Daryl
Please visit my website -> https://sbc.rictor.org/
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ElEctric_EyE
- Posts: 3260
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Thanks!
I believe I got it by blind luck! It plotted a line from (400,100) to (150,250).
It's far from complete though.
How?
I believe I got it by blind luck! It plotted a line from (400,100) to (150,250).
It's far from complete though.
8BIT wrote:
...As a quick speed enhancement, you could shift both DX and DY left until the msb of either is 1, this will reduce the loop interations...
- Attachments
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- Bresenham line.asm
- 1st draft
- (4.98 KiB) Downloaded 174 times
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ElEctric_EyE
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
I'm pretty confident it's working. In this pic I plotted 4 lines with the 4 different possible slopes:
1) (5,0) to (635,480)
2) (640,475) to (0,5)
3) (635,0) to (5,480)
4) (0,475) to (640,5)
It's pretty slow though... Time for optimizations!
1) (5,0) to (635,480)
2) (640,475) to (0,5)
3) (635,0) to (5,480)
4) (0,475) to (640,5)
It's pretty slow though... Time for optimizations!
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
ElEctric_EyE wrote:
Thanks!
I believe I got it by blind luck! It plotted a line from (400,100) to (150,250).
It's far from complete though.
How?
I believe I got it by blind luck! It plotted a line from (400,100) to (150,250).
It's far from complete though.
8BIT wrote:
...As a quick speed enhancement, you could shift both DX and DY left until the msb of either is 1, this will reduce the loop interations...
Glad to see its is at least working...optimizations will be straight forward.
Daryl
Please visit my website -> https://sbc.rictor.org/
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ElEctric_EyE
- Posts: 3260
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
No rush at all, it'll be a week before I post again...
I need a rest as well. Had too many iced coffees today and I'm burnt out, but happy I've reached my goal.
I think my earlier attempt at Bresenham lines in Verilog helped me in knowing what to look for in your code. I shouldn't have said it was blind luck. Maybe, blind luck with one eye open.
I need a rest as well. Had too many iced coffees today and I'm burnt out, but happy I've reached my goal.
I think my earlier attempt at Bresenham lines in Verilog helped me in knowing what to look for in your code. I shouldn't have said it was blind luck. Maybe, blind luck with one eye open.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
I cleaned up the code some and made a few adjustments. Still need to do the optimize on dx,dy but I want to make sure this still works first.
Give it a try when you find time. Also, I'm not really sure this can be called Bresenham Line drawing as I created the code myself.
File removed - found an error - see next post
Daryl
Give it a try when you find time. Also, I'm not really sure this can be called Bresenham Line drawing as I created the code myself.
File removed - found an error - see next post
Daryl
Please visit my website -> https://sbc.rictor.org/
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
I found and corrected an error in the first post. This post also includes the optimizations to reduce loop cycles.
The next step, if this still works, is to convert it to use multiple accumulators like the circle code.
Will await your test results. In the mean time, enjoy your break!!!
Daryl
The next step, if this still works, is to convert it to use multiple accumulators like the circle code.
Will await your test results. In the mean time, enjoy your break!!!
Daryl
- Attachments
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- Line16.asm
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ElEctric_EyE
- Posts: 3260
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Cool, I'll try it out tonight. Thanks!
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ElEctric_EyE
- Posts: 3260
- Joined: 02 Mar 2009
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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Ok, finally had a chance to plug your code in...
First, As65 has an issue with 'bcc loop1' on line 48, loop1 is undefined. I assumed it was 'bcc loop2' and went forward with testing the speed with the same 4 lines as before with 32+million cycles, whew that's alot!
Looks like DX and DY are skewed for the first 2 lines: (5,0) to (635,480) & (640,475) to (0,5). However the speed is way down to 4+million cycles.
EDIT:I had found 1 'BRA' opcode that the .b core doesn't have but As65 will translate it to a $0080 opcode value, which is undefined. I just now saw a second one and changed them to a 'JMP'. Retesting...
The first 2 lines are still skewed. Now for the lines with the coordinates that have been plotted correctly, they are "sloppier" although cycles for the routine are way down to 444013.
Since I modified your code, I should paste an update so we are on the same page.
First, As65 has an issue with 'bcc loop1' on line 48, loop1 is undefined. I assumed it was 'bcc loop2' and went forward with testing the speed with the same 4 lines as before with 32+million cycles, whew that's alot!
Looks like DX and DY are skewed for the first 2 lines: (5,0) to (635,480) & (640,475) to (0,5). However the speed is way down to 4+million cycles.
EDIT:I had found 1 'BRA' opcode that the .b core doesn't have but As65 will translate it to a $0080 opcode value, which is undefined. I just now saw a second one and changed them to a 'JMP'. Retesting...
The first 2 lines are still skewed. Now for the lines with the coordinates that have been plotted correctly, they are "sloppier" although cycles for the routine are way down to 444013.
Since I modified your code, I should paste an update so we are on the same page.
- Attachments
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- Line16.b.asm
- (4.68 KiB) Downloaded 153 times
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
The BCC loop1 was correct. I somehow erased the loop1 label. It has been added back. That should fix the skewed lines. The sloppy lines might be a byproduct of my optimization. There are two sections with comments " dx,dy optimization." Try commenting these sections out to see if the sloppiness goes away. Cycles will increase again, but I have another possible option to fix that.
Two questions about the .b core.
1) Can you do branching (bcc, bne, etc) beyond 128 bytes now?
I have several places where there is this type of code:
bne label1
jmp label 2
label1 next opcode
because label 2 was just beyond the +/- 128 byte window.
2) Does the BIT command now place bit15 and bit14 in the N an V flags?
If the optimizations are causing the sloppieness, I might be able to use the BIT command to improve it.
Will await your further tests.
Daryl
Two questions about the .b core.
1) Can you do branching (bcc, bne, etc) beyond 128 bytes now?
I have several places where there is this type of code:
bne label1
jmp label 2
label1 next opcode
because label 2 was just beyond the +/- 128 byte window.
2) Does the BIT command now place bit15 and bit14 in the N an V flags?
If the optimizations are causing the sloppieness, I might be able to use the BIT command to improve it.
Will await your further tests.
Daryl
- Attachments
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- Line16.c.asm
- (4.71 KiB) Downloaded 161 times
Please visit my website -> https://sbc.rictor.org/