Bregalad wrote:
OK I admit it was dumb of me to make this pointless thread... I apologize for spamming.
I wouldn't argue that the 6502 is RISC
I would argue that it's more RISCish than
it's contemporaries.
Tor says it's become muddled. I'd say it
has always been muddled. Most of what you
argue has become associated with RISC
since RISC moves stuff out of the hardware
and into the compiler and most of what
you list (seems to me) is about making
it easier for a compiler.
But it's really only tangential to RISC.
I think it might have been more salient
to point to the read-modify-write than
indirect indexed.
To me it's always been about how atomic
the instruction set is and I don't think
that can be well defined. Depends too much
on the hardware.
I mean suppose you put in a hardware multiply.
If it's micro coded presumably that's not
RISC but what if it's a full Wallace tree?
Does that mean it's not RISC because you
could have devoted those resources to more
registers and done it in software?
I think even obviously RISC processors do
stuff like that (for ARM one example I've
often seen is barrel shifts)
I've seen it argued that the 6502 must be
RISC because it's not micro-coded
I've seen it argued that 6502 can't be RISC
because it IS micro-coded
Or it can't be RISC because it's not
Princeton architecture.
Or because it's not (truly) pipelined
(a pipeline has to be 30 deep right?)
One argument is that RISC trys to have
lots of on chip registers because they're
fast, but they've built discrete processors
that used special ram for the registers
and called them RISC, where does that put
the 6502?
So the arguments generally are pointless.
I just think of the 6502 as sort of in between
but a big step in the right direction.